diff --git a/library/altera/common/ad_serdes_clk.v b/library/altera/common/ad_serdes_clk.v index 0761bf5f7..2ed1b58f5 100644 --- a/library/altera/common/ad_serdes_clk.v +++ b/library/altera/common/ad_serdes_clk.v @@ -34,9 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// serial data output interface: serdes(x8) -// do NOT use this module AS IT IS, the sub modules must be generated inside _hw.tcl file. -// replace __*__ names with the component names `timescale 1ps/1ps @@ -157,7 +154,7 @@ module __ad_serdes_clk__ #( generate if (DEVICE_TYPE == ARRIA10) begin - __alt_serdes_clk_core__ i_core ( + __ad_serdes_clk_1__ i_core ( .rst_reset (rst), .ref_clk_clk (clk_in_p), .locked_export (up_drp_locked_int_s), @@ -181,7 +178,7 @@ module __ad_serdes_clk__ #( assign phase = 8'd0; - __alt_serdes_clk_core__ i_core ( + __ad_serdes_clk_1__ i_core ( .rst_reset (rst), .ref_clk_clk (clk_in_p), .locked_export (up_drp_locked_int_s), diff --git a/library/altera/common/ad_serdes_in.v b/library/altera/common/ad_serdes_in.v index 59183d49a..abadf7bae 100644 --- a/library/altera/common/ad_serdes_in.v +++ b/library/altera/common/ad_serdes_in.v @@ -38,13 +38,16 @@ `timescale 1ps/1ps -module ad_serdes_in #( +module __ad_serdes_in__ #( // parameters parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 0, parameter SERDES_FACTOR = 8, - parameter DATA_WIDTH = 16) ( + parameter DATA_WIDTH = 16, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group") ( // reset and clocks @@ -83,150 +86,156 @@ module ad_serdes_in #( // local parameter - localparam C5SOC = 1; + localparam ARRIA10 = 0; + localparam CYCLONE5 = 1; // internal signals wire [(DATA_WIDTH-1):0] delay_locked_s; - wire [(DATA_WIDTH-1):0] data_out_s[ 7:0]; - wire [(DATA_WIDTH-1):0] data_sel_s[ 7:0]; + wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)]; + wire [(SERDES_FACTOR-1):0] data_out_s[0:(DATA_WIDTH-1)]; // assignments assign up_drdata = 5'd0; assign delay_locked = & delay_locked_s; - assign data_s0 = data_sel_s[0]; - assign data_s1 = data_sel_s[1]; - assign data_s2 = data_sel_s[2]; - assign data_s3 = data_sel_s[3]; - assign data_s4 = data_sel_s[4]; - assign data_s5 = data_sel_s[5]; - assign data_s6 = data_sel_s[6]; - assign data_s7 = data_sel_s[7]; - // instantiations - genvar l_inst, l_order; + genvar n; + genvar i; + generate - for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data - for (l_order = 0; l_order < SERDES_FACTOR; l_order = l_order + 1) begin: g_order - assign data_sel_s[l_order][l_inst] = data_out_s[8 - SERDES_FACTOR + l_order][l_inst]; - end + if (SERDES_FACTOR == 8) begin + assign data_s7 = data_samples_s[7]; + assign data_s6 = data_samples_s[6]; + assign data_s5 = data_samples_s[5]; + assign data_s4 = data_samples_s[4]; + end else begin + assign data_s7 = 'd0; + assign data_s6 = 'd0; + assign data_s5 = 'd0; + assign data_s4 = 'd0; + end + endgenerate - if (DEVICE_TYPE == C5SOC ) begin - altlvds_rx #( - .buffer_implementation ("RAM"), - .cds_mode ("UNUSED"), - .common_rx_tx_pll ("ON"), - .data_align_rollover (4), - .data_rate ("500.0 Mbps"), - .deserialization_factor (4), - .dpa_initial_phase_value (0), - .dpll_lock_count (0), - .dpll_lock_window (0), - .enable_clock_pin_mode ("UNUSED"), - .enable_dpa_align_to_rising_edge_only ("OFF"), - .enable_dpa_calibration ("ON"), - .enable_dpa_fifo ("UNUSED"), - .enable_dpa_initial_phase_selection ("OFF"), - .enable_dpa_mode ("OFF"), - .enable_dpa_pll_calibration ("OFF"), - .enable_soft_cdr_mode ("OFF"), - .implement_in_les ("OFF"), - .inclock_boost (0), - .inclock_data_alignment ("EDGE_ALIGNED"), - .inclock_period (4000), - .inclock_phase_shift (0), - .input_data_rate (500), - .intended_device_family ("Cyclone V"), - .lose_lock_on_one_change ("UNUSED"), - .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"), - .lpm_type ("altlvds_rx"), - .number_of_channels (DATA_WIDTH), - .outclock_resource ("Regional clock"), - .pll_operation_mode ("NORMAL"), - .pll_self_reset_on_loss_lock ("UNUSED"), - .port_rx_channel_data_align ("PORT_UNUSED"), - .port_rx_data_align ("PORT_UNUSED"), - .refclk_frequency ("250.000000 MHz"), - .registered_data_align_input ("UNUSED"), - .registered_output ("ON"), - .reset_fifo_at_first_lock ("UNUSED"), - .rx_align_data_reg ("RISING_EDGE"), - .sim_dpa_is_negative_ppm_drift ("OFF"), - .sim_dpa_net_ppm_variation (0), - .sim_dpa_output_clock_phase_shift (0), - .use_coreclock_input ("OFF"), - .use_dpll_rawperror ("OFF"), - .use_external_pll ("ON"), - .use_no_phase_shift ("ON"), - .x_on_bitslip ("ON"), - .clk_src_is_pll ("off")) - i_altlvds_rx ( - .rx_inclock (clk), - .rx_in (data_in_p[l_inst]), - .rx_outclock (), - .rx_out ({data_out_s[0][l_inst], - data_out_s[1][l_inst], - data_out_s[2][l_inst], - data_out_s[3][l_inst], - data_out_s[4][l_inst], - data_out_s[5][l_inst], - data_out_s[6][l_inst], - data_out_s[7][l_inst]}), - .rx_locked (), - .dpa_pll_cal_busy (), - .dpa_pll_recal (1'b0), - .pll_areset (~locked), - .pll_phasecounterselect (), - .pll_phasedone (1'b1), - .pll_phasestep (), - .pll_phaseupdown (), - .pll_scanclk (), - .rx_cda_max (), - .rx_cda_reset ({7{1'b0}}), - .rx_channel_data_align ({7{1'b0}}), - .rx_coreclk (1'b1), - .rx_data_align (1'b0), - .rx_data_align_reset (1'b0), - .rx_data_reset (1'b0), - .rx_deskew (1'b0), - .rx_divfwdclk (), - .rx_dpa_lock_reset ({7{1'b0}}), - .rx_dpa_locked (), - .rx_dpaclock (1'b0), - .rx_dpll_enable ({7{1'b1}}), - .rx_dpll_hold ({7{1'b0}}), - .rx_dpll_reset ({7{1'b0}}), - .rx_enable (loaden), - .rx_fifo_reset ({7{1'b0}}), - .rx_pll_enable (1'b1), - .rx_readclock (1'b0), - .rx_reset ({7{1'b0}}), - .rx_syncclock (1'b0)); + assign data_s3 = data_samples_s[3]; + assign data_s2 = data_samples_s[2]; + assign data_s1 = data_samples_s[1]; + assign data_s0 = data_samples_s[0]; - end else begin - alt_serdes_in_core i_core ( - .clk_export (clk), - .div_clk_export (div_clk), - .hs_phase_export (phase), - .loaden_export (loaden), - .locked_export (locked), - .data_in_export (data_in_p[l_inst]), - .data_s_export ({data_out_s[0][l_inst], - data_out_s[1][l_inst], - data_out_s[2][l_inst], - data_out_s[3][l_inst], - data_out_s[4][l_inst], - data_out_s[5][l_inst], - data_out_s[6][l_inst], - data_out_s[7][l_inst]}), - .delay_locked_export (delay_locked_s[l_inst])); + generate + for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap + assign data_samples_s[i][n] = data_out_s[n][((SERDES_FACTOR-1)-i)]; end end endgenerate + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data + + if (DEVICE_TYPE == CYCLONE5) begin + altlvds_rx #( + .buffer_implementation ("RAM"), + .cds_mode ("UNUSED"), + .common_rx_tx_pll ("ON"), + .data_align_rollover (4), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .dpa_initial_phase_value (0), + .dpll_lock_count (0), + .dpll_lock_window (0), + .enable_clock_pin_mode ("UNUSED"), + .enable_dpa_align_to_rising_edge_only ("OFF"), + .enable_dpa_calibration ("ON"), + .enable_dpa_fifo ("UNUSED"), + .enable_dpa_initial_phase_selection ("OFF"), + .enable_dpa_mode ("OFF"), + .enable_dpa_pll_calibration ("OFF"), + .enable_soft_cdr_mode ("OFF"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .input_data_rate (500), + .intended_device_family ("Cyclone V"), + .lose_lock_on_one_change ("UNUSED"), + .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"), + .lpm_type ("altlvds_rx"), + .number_of_channels (DATA_WIDTH), + .outclock_resource ("Regional clock"), + .pll_operation_mode ("NORMAL"), + .pll_self_reset_on_loss_lock ("UNUSED"), + .port_rx_channel_data_align ("PORT_UNUSED"), + .port_rx_data_align ("PORT_UNUSED"), + .refclk_frequency ("250.000000 MHz"), + .registered_data_align_input ("UNUSED"), + .registered_output ("ON"), + .reset_fifo_at_first_lock ("UNUSED"), + .rx_align_data_reg ("RISING_EDGE"), + .sim_dpa_is_negative_ppm_drift ("OFF"), + .sim_dpa_net_ppm_variation (0), + .sim_dpa_output_clock_phase_shift (0), + .use_coreclock_input ("OFF"), + .use_dpll_rawperror ("OFF"), + .use_external_pll ("ON"), + .use_no_phase_shift ("ON"), + .x_on_bitslip ("ON"), + .clk_src_is_pll ("off")) + i_altlvds_rx ( + .rx_inclock (clk), + .rx_in (data_in_p[n]), + .rx_outclock (), + .rx_out (data_out_s[n]), + .rx_locked (), + .dpa_pll_cal_busy (), + .dpa_pll_recal (1'b0), + .pll_areset (~locked), + .pll_phasecounterselect (), + .pll_phasedone (1'b1), + .pll_phasestep (), + .pll_phaseupdown (), + .pll_scanclk (), + .rx_cda_max (), + .rx_cda_reset ({7{1'b0}}), + .rx_channel_data_align ({7{1'b0}}), + .rx_coreclk (1'b1), + .rx_data_align (1'b0), + .rx_data_align_reset (1'b0), + .rx_data_reset (1'b0), + .rx_deskew (1'b0), + .rx_divfwdclk (), + .rx_dpa_lock_reset ({7{1'b0}}), + .rx_dpa_locked (), + .rx_dpaclock (1'b0), + .rx_dpll_enable ({7{1'b1}}), + .rx_dpll_hold ({7{1'b0}}), + .rx_dpll_reset ({7{1'b0}}), + .rx_enable (loaden), + .rx_fifo_reset ({7{1'b0}}), + .rx_pll_enable (1'b1), + .rx_readclock (1'b0), + .rx_reset ({7{1'b0}}), + .rx_syncclock (1'b0)); + end + + if (DEVICE_TYPE == ARRIA10) begin + __ad_serdes_in_1__ i_core ( + .clk_export (clk), + .div_clk_export (div_clk), + .hs_phase_export (phase), + .loaden_export (loaden), + .locked_export (locked), + .data_in_export (data_in_p[n]), + .data_s_export (data_out_s[n]), + .delay_locked_export (delay_locked_s[n])); + end + + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/altera/common/ad_serdes_out.v b/library/altera/common/ad_serdes_out.v index fd5cad778..47298a0dc 100644 --- a/library/altera/common/ad_serdes_out.v +++ b/library/altera/common/ad_serdes_out.v @@ -34,44 +34,45 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// serial data output interface: serdes(x8) `timescale 1ps/1ps -module ad_serdes_out #( +module __ad_serdes_out__ #( parameter DEVICE_TYPE = 0, + parameter DDR_OR_SDR_N = 1, parameter SERDES_FACTOR = 8, parameter DATA_WIDTH = 16) ( // reset and clocks - input rst, - input clk, - input div_clk, - input loaden, - - // data interface - - input [(DATA_WIDTH-1):0] data_s0, - input [(DATA_WIDTH-1):0] data_s1, - input [(DATA_WIDTH-1):0] data_s2, - input [(DATA_WIDTH-1):0] data_s3, - input [(DATA_WIDTH-1):0] data_s4, - input [(DATA_WIDTH-1):0] data_s5, - input [(DATA_WIDTH-1):0] data_s6, - input [(DATA_WIDTH-1):0] data_s7, - output [(DATA_WIDTH-1):0] data_out_p, - output [(DATA_WIDTH-1):0] data_out_n); + input rst, + input clk, + input div_clk, + input loaden, + + // data interface + + input [(DATA_WIDTH-1):0] data_s0, + input [(DATA_WIDTH-1):0] data_s1, + input [(DATA_WIDTH-1):0] data_s2, + input [(DATA_WIDTH-1):0] data_s3, + input [(DATA_WIDTH-1):0] data_s4, + input [(DATA_WIDTH-1):0] data_s5, + input [(DATA_WIDTH-1):0] data_s6, + input [(DATA_WIDTH-1):0] data_s7, + output [(DATA_WIDTH-1):0] data_out_p, + output [(DATA_WIDTH-1):0] data_out_n); // local parameter - localparam C5SOC = 1; + localparam ARRIA10 = 0; + localparam CYCLONE5 = 1; // internal signals - wire [(DATA_WIDTH-1):0] data_in_s[ 7:0]; - wire [(DATA_WIDTH-1):0] data_in_s2[ 7:0]; + wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)]; + wire [(SERDES_FACTOR-1):0] data_in_s[0:(DATA_WIDTH-1)]; // defaults @@ -79,99 +80,96 @@ module ad_serdes_out #( // instantiations - assign data_in_s[0] = data_s0; - assign data_in_s[1] = data_s1; - assign data_in_s[2] = data_s2; - assign data_in_s[3] = data_s3; - assign data_in_s[4] = data_s4; - assign data_in_s[5] = data_s5; - assign data_in_s[6] = data_s6; - assign data_in_s[7] = data_s7; + genvar n; + genvar i; - genvar l_order; generate - for (l_order = 0; l_order < 8; l_order = l_order + 1) begin: g_order - assign data_in_s2[l_order] = (l_order < 8-SERDES_FACTOR) ? 1'b0 : data_in_s[l_order -8 + SERDES_FACTOR]; - end + if (SERDES_FACTOR == 8) begin + assign data_samples_s[7] = data_s7; + assign data_samples_s[6] = data_s6; + assign data_samples_s[5] = data_s5; + assign data_samples_s[4] = data_s4; + end endgenerate - genvar l_inst; - generate - for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data - if (DEVICE_TYPE == C5SOC) begin - altlvds_tx #( - .center_align_msb ("UNUSED"), - .common_rx_tx_pll ("ON"), - .coreclock_divide_by (1), - .data_rate ("500.0 Mbps"), - .deserialization_factor (4), - .differential_drive (0), - .enable_clock_pin_mode ("UNUSED"), - .implement_in_les ("OFF"), - .inclock_boost (0), - .inclock_data_alignment ("EDGE_ALIGNED"), - .inclock_period (4000), - .inclock_phase_shift (0), - .intended_device_family ("Cyclone V"), - .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"), - .lpm_type ("altlvds_tx"), - .multi_clock ("OFF"), - .number_of_channels (DATA_WIDTH), - .outclock_alignment ("EDGE_ALIGNED"), - .outclock_divide_by (2), - .outclock_duty_cycle (50), - .outclock_multiply_by (1), - .outclock_phase_shift (0), - .outclock_resource ("Regional clock"), - .output_data_rate (500), - .pll_compensation_mode ("AUTO"), - .pll_self_reset_on_loss_lock ("OFF"), - .preemphasis_setting (0), - .refclk_frequency ("250.000000 MHz"), - .registered_input ("TX_CORECLK"), - .use_external_pll ("ON"), - .use_no_phase_shift ("ON"), - .vod_setting (0), - .clk_src_is_pll ("off")) - i_altlvds_tx ( - .tx_inclock (clk), - .tx_coreclock (div_clk), - .tx_in ({data_in_s2[0][l_inst], - data_in_s2[1][l_inst], - data_in_s2[2][l_inst], - data_in_s2[3][l_inst], - data_in_s2[4][l_inst], - data_in_s2[5][l_inst], - data_in_s2[6][l_inst], - data_in_s2[7][l_inst]}), - .tx_outclock (), - .tx_out (data_out_p[l_inst]), - .tx_locked (), - .pll_areset (1'b0), - .sync_inclock (1'b0), - .tx_data_reset (1'b0), - .tx_enable (loaden), - .tx_pll_enable (1'b1), - .tx_syncclock (1'b0)); + assign data_samples_s[3] = data_s3; + assign data_samples_s[2] = data_s2; + assign data_samples_s[1] = data_s1; + assign data_samples_s[0] = data_s0; - end else begin - alt_serdes_out_core i_core ( - .clk_export (clk), - .div_clk_export (div_clk), - .loaden_export (loaden), - .data_out_export (data_out_p[l_inst]), - .data_s_export ({data_in_s2[0][l_inst], - data_in_s2[1][l_inst], - data_in_s2[2][l_inst], - data_in_s2[3][l_inst], - data_in_s2[4][l_inst], - data_in_s2[5][l_inst], - data_in_s2[6][l_inst], - data_in_s2[7][l_inst]})); + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap + for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples + assign data_in_s[n][((SERDES_FACTOR-1)-i)] = data_samples_s[i][n]; end end endgenerate + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data + + if (DEVICE_TYPE == CYCLONE5) begin + altlvds_tx #( + .center_align_msb ("UNUSED"), + .common_rx_tx_pll ("ON"), + .coreclock_divide_by (1), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .differential_drive (0), + .enable_clock_pin_mode ("UNUSED"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .intended_device_family ("Cyclone V"), + .lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"), + .lpm_type ("altlvds_tx"), + .multi_clock ("OFF"), + .number_of_channels (DATA_WIDTH), + .outclock_alignment ("EDGE_ALIGNED"), + .outclock_divide_by (2), + .outclock_duty_cycle (50), + .outclock_multiply_by (1), + .outclock_phase_shift (0), + .outclock_resource ("Regional clock"), + .output_data_rate (500), + .pll_compensation_mode ("AUTO"), + .pll_self_reset_on_loss_lock ("OFF"), + .preemphasis_setting (0), + .refclk_frequency ("250.000000 MHz"), + .registered_input ("TX_CORECLK"), + .use_external_pll ("ON"), + .use_no_phase_shift ("ON"), + .vod_setting (0), + .clk_src_is_pll ("off")) + i_altlvds_tx ( + .tx_inclock (clk), + .tx_coreclock (div_clk), + .tx_in (data_in_s[n]), + .tx_outclock (), + .tx_out (data_out_p[n]), + .tx_locked (), + .pll_areset (1'b0), + .sync_inclock (1'b0), + .tx_data_reset (1'b0), + .tx_enable (loaden), + .tx_pll_enable (1'b1), + .tx_syncclock (1'b0)); + end + + if (DEVICE_TYPE == ARRIA10) begin + __ad_serdes_out_1__ i_core ( + .clk_export (clk), + .div_clk_export (div_clk), + .loaden_export (loaden), + .data_out_export (data_out_p[n]), + .data_s_export (data_in_s[n])); + end + + end + endgenerate + endmodule // *************************************************************************** diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v index 45d930c2d..e3940d312 100644 --- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v @@ -403,7 +403,14 @@ module axi_ad9361_lvds_if #( .data_s6 (), .data_s7 (), .data_in_p (rx_data_in_p), - .data_in_n (rx_data_in_n)); + .data_in_n (rx_data_in_n), + .up_clk (1'd0), + .up_dld (6'd0), + .up_dwdata (30'd0), + .up_drdata (), + .delay_clk (1'd0), + .delay_rst (1'd0), + .delay_locked ()); // receive frame interface @@ -427,7 +434,14 @@ module axi_ad9361_lvds_if #( .data_s6 (), .data_s7 (), .data_in_p (rx_frame_in_p), - .data_in_n (rx_frame_in_n)); + .data_in_n (rx_frame_in_n), + .up_clk (1'd0), + .up_dld (6'd0), + .up_dwdata (30'd0), + .up_drdata (), + .delay_clk (1'd0), + .delay_rst (1'd0), + .delay_locked ()); // transmit data interface diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index 8927db039..af6ea017b 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -69,116 +69,116 @@ module axi_ad9361 #( // physical interface (receive-cmos) - input rx_clk_in, - input rx_frame_in, - input [11:0] rx_data_in, + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, // physical interface (transmit-lvds) - output tx_clk_out_p, - output tx_clk_out_n, - output tx_frame_out_p, - output tx_frame_out_n, - output [ 5:0] tx_data_out_p, - output [ 5:0] tx_data_out_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, // physical interface (transmit-cmos) - output tx_clk_out, - output tx_frame_out, - output [11:0] tx_data_out, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, // ensm control - output enable, - output txnrx, + output enable, + output txnrx, // transmit master/slave - input dac_sync_in, - output dac_sync_out, + input dac_sync_in, + output dac_sync_out, // tdd sync - input tdd_sync, - output tdd_sync_cntr, + input tdd_sync, + output tdd_sync_cntr, // delay clock - input delay_clk, + input delay_clk, // master interface - output l_clk, - input clk, - output rst, + output l_clk, + input clk, + output rst, // dma interface - output adc_enable_i0, - output reg adc_valid_i0, - output reg [15:0] adc_data_i0, - output adc_enable_q0, - output reg adc_valid_q0, - output reg [15:0] adc_data_q0, - output adc_enable_i1, - output reg adc_valid_i1, - output reg [15:0] adc_data_i1, - output adc_enable_q1, - output reg adc_valid_q1, - output reg [15:0] adc_data_q1, - input adc_dovf, - input adc_dunf, - output adc_r1_mode, + output adc_enable_i0, + output adc_valid_i0, + output [15:0] adc_data_i0, + output adc_enable_q0, + output adc_valid_q0, + output [15:0] adc_data_q0, + output adc_enable_i1, + output adc_valid_i1, + output [15:0] adc_data_i1, + output adc_enable_q1, + output adc_valid_q1, + output [15:0] adc_data_q1, + input adc_dovf, + input adc_dunf, + output adc_r1_mode, - output dac_enable_i0, - output reg dac_valid_i0, - input [15:0] dac_data_i0, - output dac_enable_q0, - output reg dac_valid_q0, - input [15:0] dac_data_q0, - output dac_enable_i1, - output reg dac_valid_i1, - input [15:0] dac_data_i1, - output dac_enable_q1, - output reg dac_valid_q1, - input [15:0] dac_data_q1, - input dac_dovf, - input dac_dunf, - output dac_r1_mode, + output dac_enable_i0, + output dac_valid_i0, + input [15:0] dac_data_i0, + output dac_enable_q0, + output dac_valid_q0, + input [15:0] dac_data_q0, + output dac_enable_i1, + output dac_valid_i1, + input [15:0] dac_data_i1, + output dac_enable_q1, + output dac_valid_q1, + input [15:0] dac_data_q1, + input dac_dovf, + input dac_dunf, + output dac_r1_mode, // axi interface - input s_axi_aclk, - input s_axi_aresetn, - input s_axi_awvalid, - input [31:0] s_axi_awaddr, - input [ 2:0] s_axi_awprot, - output s_axi_awready, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [31:0] s_axi_araddr, - input [ 2:0] s_axi_arprot, - output s_axi_arready, - output s_axi_rvalid, - output [31:0] s_axi_rdata, - output [ 1:0] s_axi_rresp, - input s_axi_rready, + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, // gpio - input up_enable, - input up_txnrx, - input [31:0] up_dac_gpio_in, - output [31:0] up_dac_gpio_out, - input [31:0] up_adc_gpio_in, - output [31:0] up_adc_gpio_out); + input up_enable, + input up_txnrx, + input [31:0] up_dac_gpio_in, + output [31:0] up_dac_gpio_out, + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out); // derived parameters @@ -193,6 +193,18 @@ module axi_ad9361 #( // internal registers + reg adc_valid_i0_int = 'd0; + reg adc_valid_q0_int = 'd0; + reg adc_valid_i1_int = 'd0; + reg adc_valid_q1_int = 'd0; + reg [15:0] adc_data_i0_int = 'd0; + reg [15:0] adc_data_q0_int = 'd0; + reg [15:0] adc_data_i1_int = 'd0; + reg [15:0] adc_data_q1_int = 'd0; + reg dac_valid_i0_int = 'd0; + reg dac_valid_q0_int = 'd0; + reg dac_valid_i1_int = 'd0; + reg dac_valid_q1_int = 'd0; reg up_wack = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; @@ -260,7 +272,7 @@ module axi_ad9361 #( wire tdd_rx_rf_en_s; wire tdd_tx_rf_en_s; wire [ 7:0] tdd_status_s; - + // signal name changes assign up_clk = s_axi_aclk; @@ -406,22 +418,40 @@ module axi_ad9361 #( end endgenerate + assign adc_valid_i0 = adc_valid_i0_int; + assign adc_valid_q0 = adc_valid_q0_int; + assign adc_valid_i1 = adc_valid_i1_int; + assign adc_valid_q1 = adc_valid_q1_int; + always @(posedge clk) begin + adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s; + adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s; + adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s; + adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s; + end - dac_valid_i0 <= tdd_tx_valid_s & dac_valid_i0_s; - dac_valid_q0 <= tdd_tx_valid_s & dac_valid_q0_s; - dac_valid_i1 <= tdd_tx_valid_s & dac_valid_i1_s; - dac_valid_q1 <= tdd_tx_valid_s & dac_valid_q1_s; + assign adc_data_i0 = adc_data_i0_int; + assign adc_data_q0 = adc_data_q0_int; + assign adc_data_i1 = adc_data_i1_int; + assign adc_data_q1 = adc_data_q1_int; - adc_valid_i0 <= tdd_rx_valid_s & adc_valid_i0_s; - adc_valid_q0 <= tdd_rx_valid_s & adc_valid_q0_s; - adc_valid_i1 <= tdd_rx_valid_s & adc_valid_i1_s; - adc_valid_q1 <= tdd_rx_valid_s & adc_valid_q1_s; - adc_data_i0 <= adc_data_i0_s; - adc_data_q0 <= adc_data_q0_s; - adc_data_i1 <= adc_data_i1_s; - adc_data_q1 <= adc_data_q1_s; + always @(posedge clk) begin + adc_data_i0_int <= adc_data_i0_s; + adc_data_q0_int <= adc_data_q0_s; + adc_data_i1_int <= adc_data_i1_s; + adc_data_q1_int <= adc_data_q1_s; + end + assign dac_valid_i0 = dac_valid_i0_int; + assign dac_valid_q0 = dac_valid_q0_int; + assign dac_valid_i1 = dac_valid_i1_int; + assign dac_valid_q1 = dac_valid_q1_int; + + always @(posedge clk) begin + dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s; + dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s; + dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s; + dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s; end // tdd diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index d8696c7a9..c14fff648 100644 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -13,22 +13,16 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9361 # files -add_fileset quartus_synth QUARTUS_SYNTH "" "" +add_fileset quartus_synth QUARTUS_SYNTH "p_axi_ad9361_fset" "" set_fileset_property quartus_synth TOP_LEVEL axi_ad9361 add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v -add_fileset_file ad_serdes_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v -add_fileset_file ad_serdes_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v -add_fileset_file ad_serdes_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v -add_fileset_file ad_cmos_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v -add_fileset_file ad_cmos_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_in.v -add_fileset_file ad_cmos_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_out.v add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v +add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v -add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v add_fileset_file ad_addsub.v VERILOG PATH $ad_hdl_dir/library/common/ad_addsub.v add_fileset_file ad_tdd_control.v VERILOG PATH $ad_hdl_dir/library/common/ad_tdd_control.v @@ -57,79 +51,33 @@ add_fileset_file axi_ad9361_constr.sdc SDC PATH axi_ad9361_constr.sdc # parameters -add_parameter ID INTEGER 0 -set_parameter_property ID DEFAULT_VALUE 0 -set_parameter_property ID DISPLAY_NAME ID -set_parameter_property ID TYPE INTEGER -set_parameter_property ID UNITS None -set_parameter_property ID HDL_PARAMETER true - -add_parameter DEVICE_TYPE INTEGER 0 -set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0 -set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE -set_parameter_property DEVICE_TYPE TYPE INTEGER -set_parameter_property DEVICE_TYPE UNITS None -set_parameter_property DEVICE_TYPE HDL_PARAMETER true - -add_parameter CMOS_OR_LVDS_N INTEGER 0 -set_parameter_property CMOS_OR_LVDS_N DEFAULT_VALUE 0 -set_parameter_property CMOS_OR_LVDS_N DISPLAY_NAME CMOS_OR_LVDS_N -set_parameter_property CMOS_OR_LVDS_N TYPE INTEGER -set_parameter_property CMOS_OR_LVDS_N UNITS None -set_parameter_property CMOS_OR_LVDS_N HDL_PARAMETER true - -add_parameter DAC_DATAPATH_DISABLE INTEGER 0 -set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0 -set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE -set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER -set_parameter_property DAC_DATAPATH_DISABLE UNITS None -set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true - -add_parameter ADC_DATAPATH_DISABLE INTEGER 0 -set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0 -set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE -set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER -set_parameter_property ADC_DATAPATH_DISABLE UNITS None -set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true - add_parameter DEVICE_FAMILY STRING set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY} set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true set_parameter_property DEVICE_FAMILY HDL_PARAMETER false set_parameter_property DEVICE_FAMILY ENABLED false -# axi4 slave interface +add_parameter ID INTEGER 0 +add_parameter MODE_1R1T INTEGER 0 +add_parameter DEVICE_TYPE INTEGER 0 +add_parameter TDD_DISABLE INTEGER 0 +add_parameter CMOS_OR_LVDS_N INTEGER 0 +add_parameter ADC_DATAPATH_DISABLE INTEGER 0 +add_parameter ADC_USERPORTS_DISABLE INTEGER 0 +add_parameter ADC_DATAFORMAT_DISABLE INTEGER 0 +add_parameter ADC_DCFILTER_DISABLE INTEGER 0 +add_parameter ADC_IQCORRECTION_DISABLE INTEGER 0 +add_parameter DAC_IODELAY_ENABLE INTEGER 0 +add_parameter DAC_DATAPATH_DISABLE INTEGER 0 +add_parameter DAC_DDS_DISABLE INTEGER 0 +add_parameter DAC_USERPORTS_DISABLE INTEGER 0 +add_parameter DAC_IQCORRECTION_DISABLE INTEGER 0 +add_parameter IO_DELAY_GROUP STRING "dev_if_delay_group" -add_interface s_axi_clock clock end -add_interface_port s_axi_clock s_axi_aclk clk Input 1 - -add_interface s_axi_reset reset end -set_interface_property s_axi_reset associatedClock s_axi_clock -add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1 - -add_interface s_axi axi4lite end -set_interface_property s_axi associatedClock s_axi_clock -set_interface_property s_axi associatedReset s_axi_reset -add_interface_port s_axi s_axi_awvalid awvalid Input 1 -add_interface_port s_axi s_axi_awaddr awaddr Input 16 -add_interface_port s_axi s_axi_awprot awprot Input 3 -add_interface_port s_axi s_axi_awready awready Output 1 -add_interface_port s_axi s_axi_wvalid wvalid Input 1 -add_interface_port s_axi s_axi_wdata wdata Input 32 -add_interface_port s_axi s_axi_wstrb wstrb Input 4 -add_interface_port s_axi s_axi_wready wready Output 1 -add_interface_port s_axi s_axi_bvalid bvalid Output 1 -add_interface_port s_axi s_axi_bresp bresp Output 2 -add_interface_port s_axi s_axi_bready bready Input 1 -add_interface_port s_axi s_axi_arvalid arvalid Input 1 -add_interface_port s_axi s_axi_araddr araddr Input 16 -add_interface_port s_axi s_axi_arprot arprot Input 3 -add_interface_port s_axi s_axi_arready arready Output 1 -add_interface_port s_axi s_axi_rvalid rvalid Output 1 -add_interface_port s_axi s_axi_rresp rresp Output 2 -add_interface_port s_axi s_axi_rdata rdata Output 32 -add_interface_port s_axi s_axi_rready rready Input 1 +# interfaces +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + # master-slave interface ad_alt_intf signal dac_sync_in input 1 @@ -223,42 +171,11 @@ ad_alt_intf signal up_dac_gpio_out output 32 ad_alt_intf signal up_adc_gpio_in input 32 ad_alt_intf signal up_adc_gpio_out output 32 -add_hdl_instance alt_ddio_in altera_gpio -set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input} -set_instance_parameter_value alt_ddio_in {SIZE} {1} -set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0} -set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO} - -add_hdl_instance alt_ddio_out altera_gpio -set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output} -set_instance_parameter_value alt_ddio_out {SIZE} {1} -set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0} -set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO} - -add_hdl_instance alt_serdes_clk_core alt_serdes -set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK} -set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1} -set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4} -set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0} - -add_hdl_instance alt_serdes_in_core alt_serdes -set_instance_parameter_value alt_serdes_in_core {MODE} {IN} -set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1} -set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4} -set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0} - -add_hdl_instance alt_serdes_out_core alt_serdes -set_instance_parameter_value alt_serdes_out_core {MODE} {OUT} -set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1} -set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4} -set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0} - # updates proc p_axi_ad9361 {} { set m_cmos_or_lvds_n [get_parameter_value CMOS_OR_LVDS_N] - set m_device_type [get_parameter_value DEVICE_TYPE] set m_device_family [get_parameter_value DEVICE_FAMILY] add_interface device_if conduit end @@ -294,14 +211,57 @@ proc p_axi_ad9361 {} { add_interface_port device_if enable enable Output 1 add_interface_port device_if txnrx txnrx Output 1 - if {$m_device_type == 1} { + if {$m_device_family == "Arria 10"} { - ## add_hdl_instance do not work here (pending altera support) + add_hdl_instance alt_serdes_clk_core alt_serdes + set_instance_parameter_value alt_serdes_clk_core {MODE} {CLK} + set_instance_parameter_value alt_serdes_clk_core {DDR_OR_SDR_N} {1} + set_instance_parameter_value alt_serdes_clk_core {SERDES_FACTOR} {4} + set_instance_parameter_value alt_serdes_clk_core {CLKIN_FREQUENCY} {250.0} + + add_hdl_instance alt_serdes_in_core alt_serdes + set_instance_parameter_value alt_serdes_in_core {MODE} {IN} + set_instance_parameter_value alt_serdes_in_core {DDR_OR_SDR_N} {1} + set_instance_parameter_value alt_serdes_in_core {SERDES_FACTOR} {4} + set_instance_parameter_value alt_serdes_in_core {CLKIN_FREQUENCY} {250.0} + + add_hdl_instance alt_serdes_out_core alt_serdes + set_instance_parameter_value alt_serdes_out_core {MODE} {OUT} + set_instance_parameter_value alt_serdes_out_core {DDR_OR_SDR_N} {1} + set_instance_parameter_value alt_serdes_out_core {SERDES_FACTOR} {4} + set_instance_parameter_value alt_serdes_out_core {CLKIN_FREQUENCY} {250.0} + + add_hdl_instance alt_ddio_in altera_gpio + set_instance_parameter_value alt_ddio_in {PIN_TYPE_GUI} {Input} + set_instance_parameter_value alt_ddio_in {SIZE} {1} + set_instance_parameter_value alt_ddio_in {gui_diff_buff} {0} + set_instance_parameter_value alt_ddio_in {gui_io_reg_mode} {DDIO} + + add_hdl_instance alt_ddio_out altera_gpio + set_instance_parameter_value alt_ddio_out {PIN_TYPE_GUI} {Output} + set_instance_parameter_value alt_ddio_out {SIZE} {1} + set_instance_parameter_value alt_ddio_out {gui_diff_buff} {0} + set_instance_parameter_value alt_ddio_out {gui_io_reg_mode} {DDIO} } - if {$m_device_type == 0} { + if {$m_device_family == "Cyclone V"} { ## add_hdl_instance do not work here (pending altera support) } } +proc p_axi_ad9361_fset {entityName} { + + ad_ip_file ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core + ad_ip_file ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core + ad_ip_file ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core + ad_ip_file ad_cmos_in.v ad_cmos_in.v ad_cmos_in_core + ad_ip_file ad_cmos_out.v ad_cmos_out.v ad_cmos_out_core + + add_fileset_file ad_serdes_in.v VERILOG PATH ad_serdes_in.v + add_fileset_file ad_serdes_out.v VERILOG PATH ad_serdes_out.v + add_fileset_file ad_serdes_clk.v VERILOG PATH ad_serdes_clk.v + add_fileset_file ad_cmos_in.v VERILOG PATH ad_cmos_in.v + add_fileset_file ad_cmos_out.v VERILOG PATH ad_cmos_out.v +} + diff --git a/library/scripts/adi_ip_alt.tcl b/library/scripts/adi_ip_alt.tcl index 3fcc3cba8..a26b5336d 100644 --- a/library/scripts/adi_ip_alt.tcl +++ b/library/scripts/adi_ip_alt.tcl @@ -89,3 +89,60 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } { close $fp_target } +proc ad_ip_intf_s_axi {aclk arstn} { + + add_interface s_axi_clock clock end + add_interface_port s_axi_clock ${aclk} clk Input 1 + + add_interface s_axi_reset reset end + set_interface_property s_axi_reset associatedClock s_axi_clock + add_interface_port s_axi_reset ${arstn} reset_n Input 1 + + add_interface s_axi axi4lite end + set_interface_property s_axi associatedClock s_axi_clock + set_interface_property s_axi associatedReset s_axi_reset + add_interface_port s_axi s_axi_awvalid awvalid Input 1 + add_interface_port s_axi s_axi_awaddr awaddr Input 16 + add_interface_port s_axi s_axi_awprot awprot Input 3 + add_interface_port s_axi s_axi_awready awready Output 1 + add_interface_port s_axi s_axi_wvalid wvalid Input 1 + add_interface_port s_axi s_axi_wdata wdata Input 32 + add_interface_port s_axi s_axi_wstrb wstrb Input 4 + add_interface_port s_axi s_axi_wready wready Output 1 + add_interface_port s_axi s_axi_bvalid bvalid Output 1 + add_interface_port s_axi s_axi_bresp bresp Output 2 + add_interface_port s_axi s_axi_bready bready Input 1 + add_interface_port s_axi s_axi_arvalid arvalid Input 1 + add_interface_port s_axi s_axi_araddr araddr Input 16 + add_interface_port s_axi s_axi_arprot arprot Input 3 + add_interface_port s_axi s_axi_arready arready Output 1 + add_interface_port s_axi s_axi_rvalid rvalid Output 1 + add_interface_port s_axi s_axi_rresp rresp Output 2 + add_interface_port s_axi s_axi_rdata rdata Output 32 + add_interface_port s_axi s_axi_rready rready Input 1 +} + +proc ad_ip_file {ifile ofile flist} { + + global ad_hdl_dir + + set srcfile [open ${ad_hdl_dir}/library/altera/common/${ifile} r] + set dstfile [open ${ofile} w] + + regsub {\..$} $ifile {} imodule + regsub {\..$} $ofile {} omodule + + while {[gets $srcfile srcline] >= 0} { + regsub __${imodule}__ $srcline $omodule dstline + set index 0 + foreach fword $flist { + incr index + regsub __${imodule}_${index}__ $dstline $fword dstline + } + puts $dstfile $dstline + } + + close $srcfile + close $dstfile +} +