From a9cc8f6c91a93e73f9c0ffd881056d84a0f85b83 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 8 Jan 2015 10:35:59 -0500 Subject: [PATCH] ad9739a_fmc: added --- .../ad9739a_fmc/common/ad9739a_fmc_bd.tcl | 256 ++++++++++++++ projects/ad9739a_fmc/zc706/system_bd.tcl | 4 + projects/ad9739a_fmc/zc706/system_constr.xdc | 90 +++++ projects/ad9739a_fmc/zc706/system_project.tcl | 17 + projects/ad9739a_fmc/zc706/system_top.v | 330 ++++++++++++++++++ 5 files changed, 697 insertions(+) create mode 100644 projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl create mode 100644 projects/ad9739a_fmc/zc706/system_bd.tcl create mode 100644 projects/ad9739a_fmc/zc706/system_constr.xdc create mode 100644 projects/ad9739a_fmc/zc706/system_project.tcl create mode 100644 projects/ad9739a_fmc/zc706/system_top.v diff --git a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl new file mode 100644 index 000000000..ae5e796af --- /dev/null +++ b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl @@ -0,0 +1,256 @@ + + source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl + + # dac interface + + set dac_clk_in_p [create_bd_port -dir I dac_clk_in_p] + set dac_clk_in_n [create_bd_port -dir I dac_clk_in_n] + set dac_clk_out_p [create_bd_port -dir O dac_clk_out_p] + set dac_clk_out_n [create_bd_port -dir O dac_clk_out_n] + set dac_frame_out_p [create_bd_port -dir O dac_frame_out_p] + set dac_frame_out_n [create_bd_port -dir O dac_frame_out_n] + set dac_data_out_p [create_bd_port -dir O -from 15 -to 0 dac_data_out_p] + set dac_data_out_n [create_bd_port -dir O -from 15 -to 0 dac_data_out_n] + + # adc interface + + set adc_clk_in_p [create_bd_port -dir I adc_clk_in_p] + set adc_clk_in_n [create_bd_port -dir I adc_clk_in_n] + set adc_or_in_p [create_bd_port -dir I adc_or_in_p] + set adc_or_in_n [create_bd_port -dir I adc_or_in_n] + set adc_data_in_p [create_bd_port -dir I -from 13 -to 0 adc_data_in_p] + set adc_data_in_n [create_bd_port -dir I -from 13 -to 0 adc_data_in_n] + + # reference clock + + set ref_clk [create_bd_port -dir O ref_clk] + + # dma interface + + set dac_clk [create_bd_port -dir O dac_clk] + set dac_valid_0 [create_bd_port -dir O dac_valid_0] + set dac_enable_0 [create_bd_port -dir O dac_enable_0] + set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] + set dac_valid_1 [create_bd_port -dir O dac_valid_1] + set dac_enable_1 [create_bd_port -dir O dac_enable_1] + set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] + set dac_dma_rd [create_bd_port -dir I dac_dma_rd] + set dac_dma_rdata [create_bd_port -dir O -from 63 -to 0 dac_dma_rdata] + + set adc_clk [create_bd_port -dir O adc_clk] + set adc_valid_0 [create_bd_port -dir O adc_valid_0] + set adc_enable_0 [create_bd_port -dir O adc_enable_0] + set adc_data_0 [create_bd_port -dir O -from 15 -to 0 adc_data_0] + set adc_valid_1 [create_bd_port -dir O adc_valid_1] + set adc_enable_1 [create_bd_port -dir O adc_enable_1] + set adc_data_1 [create_bd_port -dir O -from 15 -to 0 adc_data_1] + set adc_dma_wr [create_bd_port -dir I adc_dma_wr] + set adc_dma_sync [create_bd_port -dir I adc_dma_sync] + set adc_dma_wdata [create_bd_port -dir I -from 31 -to 0 adc_dma_wdata] + + # interrupts + + set ad9122_dma_irq [create_bd_port -dir O ad9122_dma_irq] + set ad9643_dma_irq [create_bd_port -dir O ad9643_dma_irq] + + # dac peripherals + + set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122] + + set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9122_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma + set_property -dict [list CONFIG.C_FIFO_SIZE {64}] $axi_ad9122_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma + set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9122_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9122_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma + +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9122_dma +} + + # adc peripherals + + set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643] + + set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9643_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma + set_property -dict [list CONFIG.C_FIFO_SIZE {64}] $axi_ad9643_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9643_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9643_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma + +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9643_dma +} + +if {$sys_zynq == 0} { + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9643_dma +} + + # additions to default configuration + + set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect + +if {$sys_zynq == 0} { + set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect +} + +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +} + +# reference clock shared with audio clock + + set_property -dict [list CONFIG.CLKOUT2_USED {true}] $sys_audio_clkgen + set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {30.3030}] $sys_audio_clkgen + +# connections (dac) + + connect_bd_net -net dac_div_clk [get_bd_ports dac_clk] [get_bd_pins axi_ad9122/dac_div_clk] + connect_bd_net -net dac_div_clk [get_bd_pins axi_ad9122_dma/fifo_rd_clk] + + connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_ports dac_clk_in_p] [get_bd_pins axi_ad9122/dac_clk_in_p] + connect_bd_net -net axi_ad9122_dac_clk_in_n [get_bd_ports dac_clk_in_n] [get_bd_pins axi_ad9122/dac_clk_in_n] + connect_bd_net -net axi_ad9122_dac_clk_out_p [get_bd_ports dac_clk_out_p] [get_bd_pins axi_ad9122/dac_clk_out_p] + connect_bd_net -net axi_ad9122_dac_clk_out_n [get_bd_ports dac_clk_out_n] [get_bd_pins axi_ad9122/dac_clk_out_n] + connect_bd_net -net axi_ad9122_dac_frame_out_p [get_bd_ports dac_frame_out_p] [get_bd_pins axi_ad9122/dac_frame_out_p] + connect_bd_net -net axi_ad9122_dac_frame_out_n [get_bd_ports dac_frame_out_n] [get_bd_pins axi_ad9122/dac_frame_out_n] + connect_bd_net -net axi_ad9122_dac_data_out_p [get_bd_ports dac_data_out_p] [get_bd_pins axi_ad9122/dac_data_out_p] + connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_ports dac_data_out_n] [get_bd_pins axi_ad9122/dac_data_out_n] + + connect_bd_net -net axi_ad9122_dac_valid_0 [get_bd_pins axi_ad9122/dac_valid_0] [get_bd_ports dac_valid_0] + connect_bd_net -net axi_ad9122_dac_enable_0 [get_bd_pins axi_ad9122/dac_enable_0] [get_bd_ports dac_enable_0] + connect_bd_net -net axi_ad9122_dac_ddata_0 [get_bd_pins axi_ad9122/dac_ddata_0] [get_bd_ports dac_ddata_0] + connect_bd_net -net axi_ad9122_dac_valid_1 [get_bd_pins axi_ad9122/dac_valid_1] [get_bd_ports dac_valid_1] + connect_bd_net -net axi_ad9122_dac_enable_1 [get_bd_pins axi_ad9122/dac_enable_1] [get_bd_ports dac_enable_1] + connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122/dac_ddata_1] [get_bd_ports dac_ddata_1] + connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow] + + connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_dma_rd] + connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_dma_rdata] + connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_ports ad9122_dma_irq] + + # connections (adc) + + p_sys_wfifo [current_bd_instance .] sys_wfifo 32 64 + + connect_bd_net -net adc_clk [get_bd_ports adc_clk] [get_bd_pins axi_ad9643/adc_clk] [get_bd_pins sys_wfifo/m_clk] + connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo/s_clk] [get_bd_pins axi_ad9643_dma/fifo_wr_clk] [get_bd_pins axi_ad9643/delay_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo/rstn] $sys_100m_resetn_source + + connect_bd_net -net axi_ad9643_adc_clk_in_p [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9643/adc_clk_in_p] + connect_bd_net -net axi_ad9643_adc_clk_in_n [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9643/adc_clk_in_n] + connect_bd_net -net axi_ad9643_adc_or_in_p [get_bd_ports adc_or_in_p] [get_bd_pins axi_ad9643/adc_or_in_p] + connect_bd_net -net axi_ad9643_adc_or_in_n [get_bd_ports adc_or_in_n] [get_bd_pins axi_ad9643/adc_or_in_n] + connect_bd_net -net axi_ad9643_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9643/adc_data_in_p] + connect_bd_net -net axi_ad9643_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9643/adc_data_in_n] + + connect_bd_net -net axi_ad9643_adc_valid_0 [get_bd_ports adc_valid_0] [get_bd_pins axi_ad9643/adc_valid_0] + connect_bd_net -net axi_ad9643_adc_enable_0 [get_bd_ports adc_enable_0] [get_bd_pins axi_ad9643/adc_enable_0] + connect_bd_net -net axi_ad9643_adc_data_0 [get_bd_ports adc_data_0] [get_bd_pins axi_ad9643/adc_data_0] + connect_bd_net -net axi_ad9643_adc_valid_1 [get_bd_ports adc_valid_1] [get_bd_pins axi_ad9643/adc_valid_1] + connect_bd_net -net axi_ad9643_adc_enable_1 [get_bd_ports adc_enable_1] [get_bd_pins axi_ad9643/adc_enable_1] + connect_bd_net -net axi_ad9643_adc_data_1 [get_bd_ports adc_data_1] [get_bd_pins axi_ad9643/adc_data_1] + connect_bd_net -net axi_ad9643_adc_dovf [get_bd_pins axi_ad9643/adc_dovf] [get_bd_pins sys_wfifo/m_wovf] + + connect_bd_net -net axi_ad9643_fifo_wr [get_bd_ports adc_dma_wr] [get_bd_pins sys_wfifo/m_wr] + connect_bd_net -net axi_ad9643_fifo_wdata [get_bd_ports adc_dma_wdata] [get_bd_pins sys_wfifo/m_wdata] + + connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins sys_wfifo/s_wr] [get_bd_pins axi_ad9643_dma/fifo_wr_en] + connect_bd_net -net axi_ad9643_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9643_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din] + connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_ports ad9643_dma_irq] + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9643/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9643_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122_dma/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9643/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9643_dma/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/s_axi_aresetn] + +# interconnect (mem/dac) + +if {$sys_zynq == 0 } { + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn] +} else { + connect_bd_intf_net -intf_net axi_ad9122_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP2] [get_bd_intf_pins axi_ad9122_dma/m_src_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk] + connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn] +} + +# interconnect (mem/adc) + +if {$sys_zynq == 0 } { + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn] +} else { + connect_bd_intf_net -intf_net axi_ad9643_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk] + connect_bd_net -net sys_200m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn] +} + + # ila (adc) + + set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_adc] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc + set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc + set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc + set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc + set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc + set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc + + connect_bd_net -net sys_200m_clk [get_bd_pins ila_adc/clk] + connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins ila_adc/PROBE0] + connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins ila_adc/PROBE1] + + # reference clock + + connect_bd_net -net fmcomms1_ref_clk [get_bd_pins sys_audio_clkgen/clk_out2] [get_bd_ports ref_clk] + + # address map + + create_bd_addr_seg -range 0x00010000 -offset 0x74200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122/s_axi/axi_lite] SEG_data_ad9122 + create_bd_addr_seg -range 0x00010000 -offset 0x79020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643/s_axi/axi_lite] SEG_data_ad9643 + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9643_dma/s_axi/axi_lite] SEG_data_ad9122_dma + create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9643_dma + +if {$sys_zynq == 0} { + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl +} else { + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm +} diff --git a/projects/ad9739a_fmc/zc706/system_bd.tcl b/projects/ad9739a_fmc/zc706/system_bd.tcl new file mode 100644 index 000000000..5f9cc885f --- /dev/null +++ b/projects/ad9739a_fmc/zc706/system_bd.tcl @@ -0,0 +1,4 @@ + + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl + source ../common/fmcomms1_bd.tcl + diff --git a/projects/ad9739a_fmc/zc706/system_constr.xdc b/projects/ad9739a_fmc/zc706/system_constr.xdc new file mode 100644 index 000000000..09326a7eb --- /dev/null +++ b/projects/ad9739a_fmc/zc706/system_constr.xdc @@ -0,0 +1,90 @@ + +# reference + +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P +set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N + +# dac + +set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P +set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P +set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P +set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N +set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P +set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N +set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P +set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P +set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N + +# adc + +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P +set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P +set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N +set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N + +# clocks + +create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p] +create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p] +create_clock -name dac_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk] + +set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9643_dma/inst/i_request_arb/i_src_dma_fifo/overflow_reg/C] \ + -to [get_pins i_system_wrapper/system_i/sys_wfifo/wfifo_ctl/inst/m_wovf_m1_reg/D] diff --git a/projects/ad9739a_fmc/zc706/system_project.tcl b/projects/ad9739a_fmc/zc706/system_project.tcl new file mode 100644 index 000000000..f9df0238b --- /dev/null +++ b/projects/ad9739a_fmc/zc706/system_project.tcl @@ -0,0 +1,17 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create fmcomms1_zc706 +adi_project_files fmcomms1_zc706 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + +adi_project_run fmcomms1_zc706 + + diff --git a/projects/ad9739a_fmc/zc706/system_top.v b/projects/ad9739a_fmc/zc706/system_top.v new file mode 100644 index 000000000..a40046a09 --- /dev/null +++ b/projects/ad9739a_fmc/zc706/system_top.v @@ -0,0 +1,330 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + dac_clk_in_p, + dac_clk_in_n, + dac_clk_out_p, + dac_clk_out_n, + dac_frame_out_p, + dac_frame_out_n, + dac_data_out_p, + dac_data_out_n, + + adc_clk_in_p, + adc_clk_in_n, + adc_or_in_p, + adc_or_in_n, + adc_data_in_p, + adc_data_in_n, + + ref_clk_out_p, + ref_clk_out_n, + + iic_scl, + iic_sda); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + input dac_clk_in_p; + input dac_clk_in_n; + output dac_clk_out_p; + output dac_clk_out_n; + output dac_frame_out_p; + output dac_frame_out_n; + output [15:0] dac_data_out_p; + output [15:0] dac_data_out_n; + + input adc_clk_in_p; + input adc_clk_in_n; + input adc_or_in_p; + input adc_or_in_n; + input [13:0] adc_data_in_p; + input [13:0] adc_data_in_n; + + output ref_clk_out_p; + output ref_clk_out_n; + + inout iic_scl; + inout iic_sda; + + // internal registers + + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg dac_dma_rd = 'd0; + reg adc_data_cnt = 'd0; + reg adc_dma_wr = 'd0; + reg [31:0] adc_dma_wdata = 'd0; + + // internal signals + + wire [14:0] gpio_i; + wire [14:0] gpio_o; + wire [14:0] gpio_t; + wire dac_clk; + wire dac_valid_0; + wire dac_enable_0; + wire dac_valid_1; + wire dac_enable_1; + wire [63:0] dac_dma_rdata; + wire adc_clk; + wire adc_valid_0; + wire adc_enable_0; + wire [15:0] adc_data_0; + wire adc_valid_1; + wire adc_enable_1; + wire [15:0] adc_data_1; + wire ref_clk; + wire oddr_ref_clk; + wire [15:0] ps_intrs; + + // instantiations + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE"), + .INIT (1'b0), + .SRTYPE ("ASYNC")) + i_oddr_ref_clk ( + .S (1'b0), + .CE (1'b1), + .R (1'b0), + .C (ref_clk), + .D1 (1'b1), + .D2 (1'b0), + .Q (oddr_ref_clk)); + + OBUFDS i_obufds_ref_clk ( + .I (oddr_ref_clk), + .O (ref_clk_out_p), + .OB (ref_clk_out_n)); + + ad_iobuf #( + .DATA_WIDTH(15)) + i_gpio_bd ( + .dt(gpio_t), + .di(gpio_o), + .do(gpio_i), + .dio(gpio_bd)); + + always @(posedge dac_clk) begin + dac_dma_rd <= dac_valid_0 & dac_enable_0; + dac_ddata_1[63:48] <= dac_dma_rdata[63:48]; + dac_ddata_1[47:32] <= dac_dma_rdata[63:48]; + dac_ddata_1[31:16] <= dac_dma_rdata[31:16]; + dac_ddata_1[15: 0] <= dac_dma_rdata[31:16]; + dac_ddata_0[63:48] <= dac_dma_rdata[47:32]; + dac_ddata_0[47:32] <= dac_dma_rdata[47:32]; + dac_ddata_0[31:16] <= dac_dma_rdata[15: 0]; + dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0]; + end + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt ; + case ({adc_enable_1, adc_enable_0}) + 2'b10: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]}; + end + 2'b01: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]}; + end + default: begin + adc_dma_wr <= 1'b1; + adc_dma_wdata <= {adc_data_1, adc_data_0}; + end + endcase + end + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .adc_clk (adc_clk), + .adc_clk_in_n (adc_clk_in_n), + .adc_clk_in_p (adc_clk_in_p), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_data_in_n (adc_data_in_n), + .adc_data_in_p (adc_data_in_p), + .adc_dma_sync (1'b1), + .adc_dma_wdata (adc_dma_wdata), + .adc_dma_wr (adc_dma_wr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), + .adc_or_in_n (adc_or_in_n), + .adc_or_in_p (adc_or_in_p), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), + .dac_clk_in_n (dac_clk_in_n), + .dac_clk_in_p (dac_clk_in_p), + .dac_clk_out_n (dac_clk_out_n), + .dac_clk_out_p (dac_clk_out_p), + .dac_data_out_n (dac_data_out_n), + .dac_data_out_p (dac_data_out_p), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_dma_rd (dac_dma_rd), + .dac_dma_rdata (dac_dma_rdata), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), + .dac_frame_out_n (dac_frame_out_n), + .dac_frame_out_p (dac_frame_out_p), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_0 (ps_intrs[0]), + .ps_intr_1 (ps_intrs[1]), + .ps_intr_10 (ps_intrs[10]), + .ps_intr_11 (ps_intrs[11]), + .ps_intr_12 (ps_intrs[12]), + .ps_intr_13 (ps_intrs[13]), + .ps_intr_2 (ps_intrs[2]), + .ps_intr_3 (ps_intrs[3]), + .ps_intr_4 (ps_intrs[4]), + .ps_intr_5 (ps_intrs[5]), + .ps_intr_6 (ps_intrs[6]), + .ps_intr_7 (ps_intrs[7]), + .ps_intr_8 (ps_intrs[8]), + .ps_intr_9 (ps_intrs[9]), + .ad9122_dma_irq (ps_intrs[12]), + .ad9643_dma_irq (ps_intrs[13]), + .ref_clk (ref_clk), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************