From a9c61485704d74723c48cf0bad03056ecfc8e4e4 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 4 Dec 2014 13:27:58 +0100 Subject: [PATCH] fmcomms6: Better cope with higher sample rates There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz. Signed-off-by: Lars-Peter Clausen --- projects/fmcomms6/common/fmcomms6_bd.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl index e4c88d03a..55ee7b5fb 100644 --- a/projects/fmcomms6/common/fmcomms6_bd.tcl +++ b/projects/fmcomms6/common/fmcomms6_bd.tcl @@ -65,6 +65,7 @@ set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9652_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9652_dma set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9652_dma set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma +set_property -dict [list CONFIG.C_FIFO_SIZE {8}] $axi_ad9652_dma if {$sys_zynq == 0} { @@ -87,7 +88,7 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7 + set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {170.0}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7