diff --git a/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl b/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl index 2794960f8..9e45cfe5d 100644 --- a/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl +++ b/library/altera/avl_dacfifo/avl_dacfifo_hw.tcl @@ -8,6 +8,8 @@ ad_ip_files avl_dacfifo [list\ $ad_hdl_dir/library/altera/common/ad_mem_asym.v \ $ad_hdl_dir/library/common/util_dacfifo_bypass.v \ $ad_hdl_dir/library/common/util_delay.v \ + $ad_hdl_dir/library/common/ad_b2g.v \ + $ad_hdl_dir/library/common/ad_g2b.v \ avl_dacfifo_byteenable_coder.v \ avl_dacfifo_wr.v \ avl_dacfifo_rd.v \ diff --git a/library/altera/avl_dacfifo/avl_dacfifo_rd.v b/library/altera/avl_dacfifo/avl_dacfifo_rd.v index 80c913d37..fcee04c69 100644 --- a/library/altera/avl_dacfifo/avl_dacfifo_rd.v +++ b/library/altera/avl_dacfifo/avl_dacfifo_rd.v @@ -93,49 +93,17 @@ module avl_dacfifo_rd #( wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_s; wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_address_diff_s; + wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_wr_address_b2g_s; wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_address_diff_s; wire avl_xfer_req_init_s; wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_wr_address_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_wr_address_g2b_s; + wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_g2b_s; + wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_rd_address_b2g_s; wire dac_mem_rd_enable_s; wire [DAC_DATA_WIDTH-1:0] dac_mem_data_s; - // ========================================================================== - // binary to grey conversion and grey to binary conversion for CDC circuitry - // ========================================================================== - - function [7:0] b2g; - input [7:0] b; - reg [7:0] g; - begin - g[7] = b[7]; - g[6] = b[7] ^ b[6]; - g[5] = b[6] ^ b[5]; - g[4] = b[5] ^ b[4]; - g[3] = b[4] ^ b[3]; - g[2] = b[3] ^ b[2]; - g[1] = b[2] ^ b[1]; - g[0] = b[1] ^ b[0]; - b2g = g; - end - endfunction - - - function [7:0] g2b; - input [7:0] g; - reg [7:0] b; - begin - b[7] = g[7]; - b[6] = b[7] ^ g[6]; - b[5] = b[6] ^ g[5]; - b[4] = b[5] ^ g[4]; - b[3] = b[4] ^ g[3]; - b[2] = b[3] ^ g[2]; - b[1] = b[2] ^ g[1]; - b[0] = b[1] ^ g[0]; - g2b = b; - end - endfunction // ========================================================================== // An asymmetric memory to transfer data from Avalon interface to DAC @@ -225,10 +193,16 @@ module avl_dacfifo_rd #( if (avl_mem_wr_enable == 1'b1) begin avl_mem_wr_address <= avl_mem_wr_address + 1; end - avl_mem_wr_address_g <= b2g(avl_mem_wr_address); + avl_mem_wr_address_g <= avl_mem_wr_address_b2g_s; end end + ad_b2g #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_avl_mem_wr_address_b2g ( + .din (avl_mem_wr_address), + .dout (avl_mem_wr_address_b2g_s)); + // ========================================================================== // control the FIFO to prevent overflow, underfloq is monitored // ========================================================================== @@ -252,7 +226,7 @@ module avl_dacfifo_rd #( end else begin avl_mem_rd_address_m1 <= dac_mem_rd_address_g; avl_mem_rd_address_m2 <= avl_mem_rd_address_m1; - avl_mem_rd_address <= g2b(avl_mem_rd_address_m2); + avl_mem_rd_address <= avl_mem_rd_address_g2b_s; avl_mem_address_diff <= avl_mem_address_diff_s[AVL_MEM_ADDRESS_WIDTH-1:0]; if (avl_mem_address_diff >= AVL_MEM_THRESHOLD_HI) begin avl_mem_request_data <= 1'b0; @@ -262,6 +236,11 @@ module avl_dacfifo_rd #( end end + ad_g2b #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_avl_mem_rd_address_g2b ( + .din (avl_mem_rd_address_m2), + .dout (avl_mem_rd_address_g2b_s)); // ========================================================================== // Push data from the async FIFO to the DAC // Data flow is controlled by the DAC, no back-pressure. If FIFO is not @@ -285,10 +264,16 @@ module avl_dacfifo_rd #( end else begin dac_mem_wr_address_m1 <= avl_mem_wr_address_g; dac_mem_wr_address_m2 <= dac_mem_wr_address_m1; - dac_mem_wr_address <= g2b(dac_mem_wr_address_m2); + dac_mem_wr_address <= dac_mem_wr_address_g2b_s; end end + ad_g2b #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_dac_mem_wr_address_g2b ( + .din (dac_mem_wr_address_m2), + .dout (dac_mem_wr_address_g2b_s)); + always @(posedge dac_clk) begin if (dac_reset == 1'b1) begin dac_avl_xfer_req_m2 <= 0; @@ -312,10 +297,16 @@ module avl_dacfifo_rd #( if (dac_mem_rd_enable_s == 1'b1) begin dac_mem_rd_address <= dac_mem_rd_address + 1; end - dac_mem_rd_address_g <= b2g(dac_mem_rd_address); + dac_mem_rd_address_g <= dac_mem_rd_address_b2g_s; end end + ad_b2g #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_dac_mem_rd_address_b2g ( + .din (dac_mem_rd_address), + .dout (dac_mem_rd_address_b2g_s)); + always @(posedge dac_clk) begin if (dac_reset == 1'b1) begin dac_xfer_req <= 0; diff --git a/library/altera/avl_dacfifo/avl_dacfifo_wr.v b/library/altera/avl_dacfifo/avl_dacfifo_wr.v index 5011d0b39..096094581 100644 --- a/library/altera/avl_dacfifo/avl_dacfifo_wr.v +++ b/library/altera/avl_dacfifo/avl_dacfifo_wr.v @@ -74,6 +74,7 @@ module avl_dacfifo_wr #( wire dma_mem_wea_s; wire [DMA_MEM_ADDRESS_WIDTH :0] dma_mem_address_diff_s; wire [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_rd_address_g2b_s; wire [AVL_DATA_WIDTH-1:0] avl_mem_rdata_s; wire avl_mem_fetch_wr_address_s; @@ -83,6 +84,7 @@ module avl_dacfifo_wr #( wire avl_last_transfer_req_s; wire avl_xfer_req_init_s; wire avl_pending_write_cycle_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_rd_address_b2g_s; reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_wr_address; reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_wr_address_d; @@ -117,42 +119,6 @@ module avl_dacfifo_wr #( reg avl_write_xfer_req; reg avl_write_xfer_req_d; - // binary to grey conversion - - function [7:0] b2g; - input [7:0] b; - reg [7:0] g; - begin - g[7] = b[7]; - g[6] = b[7] ^ b[6]; - g[5] = b[6] ^ b[5]; - g[4] = b[5] ^ b[4]; - g[3] = b[4] ^ b[3]; - g[2] = b[3] ^ b[2]; - g[1] = b[2] ^ b[1]; - g[0] = b[1] ^ b[0]; - b2g = g; - end - endfunction - - // grey to binary conversion - - function [7:0] g2b; - input [7:0] g; - reg [7:0] b; - begin - b[7] = g[7]; - b[6] = b[7] ^ g[6]; - b[5] = b[6] ^ g[5]; - b[4] = b[5] ^ g[4]; - b[3] = b[4] ^ g[3]; - b[2] = b[3] ^ g[2]; - b[1] = b[2] ^ g[1]; - b[0] = b[1] ^ g[0]; - g2b = b; - end - endfunction - // An asymmetric memory to transfer data from DMAC interface to AXI Memory Map // interface @@ -216,7 +182,7 @@ module avl_dacfifo_wr #( end else begin dma_mem_rd_address_m1 <= avl_mem_rd_address_g; dma_mem_rd_address_m2 <= dma_mem_rd_address_m1; - dma_mem_rd_address <= g2b(dma_mem_rd_address_m2); + dma_mem_rd_address <= dma_mem_rd_address_g2b_s; dma_mem_address_diff <= dma_mem_address_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0]; if (dma_mem_address_diff >= DMA_BUF_THRESHOLD_HI) begin dma_ready_out <= 1'b0; @@ -226,6 +192,12 @@ module avl_dacfifo_wr #( end end + ad_g2b #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_dma_mem_rd_address_g2b ( + .din (dma_mem_rd_address_m2), + .dout (dma_mem_rd_address_g2b_s)); + // last DMA beat always @(posedge dma_clk) begin @@ -285,12 +257,18 @@ module avl_dacfifo_wr #( avl_mem_rd_address <= avl_mem_rd_address + 1; end avl_data <= avl_mem_rdata_s; - avl_mem_rd_address_g <= b2g(avl_mem_rd_address); + avl_mem_rd_address_g <= avl_mem_rd_address_b2g_s; avl_write_transfer <= avl_write_transfer_s; avl_mem_readen <= avl_mem_readen_s; end end + ad_b2g #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_avl_mem_rd_address_b2g ( + .din (avl_mem_rd_address), + .dout (avl_mem_rd_address_b2g_s)); + // avalon write signaling assign avl_last_transfer_req_s = avl_last_beat_req & ~avl_mem_readen & ~avl_xfer_req;