ad_dds_sine: Cosmetic updates only

library/common/ad_dds.v

@@ -42,6 +42,7 @@ module ad_dds #(
   parameter   DISABLE = 0,
   parameter   DDS_TYPE = 1,
   parameter   CORDIC_DW = 14) (
+
   // interface
 
   input           clk,

library/common/ad_dds_1.v

@@ -86,6 +86,7 @@ module ad_dds_1 #(
         .clk (clk),
         .angle (angle_s[CORDIC_DW:1]),
         .sine (sine_s),
+        .cosine (),
         .ddata_in (1'b0),
         .ddata_out ());
 

library/common/ad_dds_cordic_pipe.v

@@ -39,11 +39,14 @@ module ad_dds_cordic_pipe#(
 
   // parameters
 
+  // Range = N/A
   parameter DW = 16,
+  // Range = N/A
   parameter DELAY_DW = 1,
+  // Range = 0-(DW - 1)
   parameter SHIFT = 0) (
 
-  // interface
+  // Interface
 
                       input                          clk,
   (* keep = "TRUE" *) input                          dir,
@@ -59,33 +62,34 @@ module ad_dds_cordic_pipe#(
                       output     signed [    DW-1:0] sgn_shift_x,
                       output     signed [    DW-1:0] sgn_shift_y,
                       input             [DELAY_DW:1] data_delay_in,
-                      output            [DELAY_DW:1] data_delay_out
-  );
+                      output            [DELAY_DW:1] data_delay_out);
 
-  // internal registers
+  // Registers Declarations
 
   reg   [DELAY_DW:1] data_delay = 'd0;
 
+  // Wires Declarations
+
   wire dir_inv = ~dir;
 
-  // stage rotation
+  // Stage rotation
 
-  always @(posedge clk)
-    begin
+  always @(posedge clk) begin
     result_x <= dataa_x + ({DW{dir_inv}} ^ datab_y) + dir_inv;
     result_y <= dataa_y + ({DW{dir}}     ^ datab_x) + dir;
     result_z <= dataa_z + ({DW{dir_inv}} ^ datab_z) + dir_inv;
   end
 
-  // stage shift
+  // Stage shift
 
-  assign sgn_shift_x = result_x >>> SHIFT + 1;
-  assign sgn_shift_y = result_y >>> SHIFT + 1;
+  assign sgn_shift_x = {{SHIFT{result_x[DW-1]}}, result_x[DW-1:SHIFT]};
+  assign sgn_shift_y = {{SHIFT{result_y[DW-1]}}, result_y[DW-1:SHIFT]};
+
+  // Delay data (if used)
 
   generate
     if (DELAY_DW > 1) begin
-      always @(posedge clk)
-      begin
+      always @(posedge clk) begin
         data_delay <= data_delay_in;
       end
     end

library/common/ad_dds_sine_cordic.v

@@ -37,9 +37,9 @@
 
 module ad_dds_sine_cordic #(
 
-  // parameters
-
+  // Range = 14, 16, 18 and 20
   parameter   CORDIC_DW = 16,
+  // Range = N/A
   parameter   DELAY_DW  = 1) (
 
   // interface
@@ -47,22 +47,25 @@ module ad_dds_sine_cordic #(
   input                        clk,
   input      [CORDIC_DW-1:0]   angle,
   output reg [CORDIC_DW-1:0]   sine,
+  output reg [CORDIC_DW-1:0]   cosine,
   input      [ DELAY_DW-1:0]   ddata_in,
   output reg [ DELAY_DW-1:0]   ddata_out);
 
+  // Local Parameters
+
   // 1.647 = gain of the system
   localparam [19:0] X_VALUE_20 = 318327; // ((20^2)/2)/1.647
   localparam [17:0] X_VALUE_18 =  79582; // ((18^2)/2)/1.647
   localparam [15:0] X_VALUE_16 =  19883; // ((16^2)/2)/1.647
   localparam [13:0] X_VALUE_14 =   4970; // ((14^2)/2)/1.647
 
-  // internal registers
+  // Registers Declarations
 
   reg signed  [CORDIC_DW-1:0] x0  = 'd0;
   reg signed  [CORDIC_DW-1:0] y0  = 'd0;
   reg signed  [CORDIC_DW-1:0] z0  = 'd0;
 
-  // internal signals
+  // Wires Declarations
 
   wire        [CORDIC_DW-1:0] x_value;
   wire signed [CORDIC_DW-1:0] x_s       [0:CORDIC_DW-1];
@@ -157,27 +160,22 @@ module ad_dds_sine_cordic #(
   // first two bits represent the quadrant in the unit circle
   assign   quadrant = angle[CORDIC_DW-1:CORDIC_DW-2];
 
-  always @(posedge clk)
-  begin
-
+  always @(posedge clk) begin
     case (quadrant)
       2'b00,
-       2'b11:
-       begin
+      2'b11: begin
          x0 <= x_value;
          y0 <= 0;
          z0 <= angle;
       end
 
-       2'b01:
-       begin
+      2'b01: begin
          x0 <= 0;
          y0 <= x_value;
          z0 <= {2'b00, angle[CORDIC_DW-3:0]};
       end
 
-       2'b10:
-       begin
+      2'b10: begin
          x0 <= 0;
          y0 <= -x_value;
          z0 <= {2'b11, angle[CORDIC_DW-3:0]};
@@ -227,6 +225,7 @@ module ad_dds_sine_cordic #(
   always @(posedge clk) begin
     ddata_out <= data_in_d[CORDIC_DW-1];
     sine <= y_s[CORDIC_DW-1];
+    cosine <= x_s[CORDIC_DW-1];
   end
 
 endmodule