ad_dds_sine: Cosmetic updates only
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43f460e744
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a96d9bd3c2
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@ -42,6 +42,7 @@ module ad_dds #(
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parameter DISABLE = 0,
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parameter DISABLE = 0,
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parameter DDS_TYPE = 1,
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parameter DDS_TYPE = 1,
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parameter CORDIC_DW = 14) (
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parameter CORDIC_DW = 14) (
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// interface
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// interface
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input clk,
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input clk,
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@ -86,6 +86,7 @@ module ad_dds_1 #(
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.clk (clk),
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.clk (clk),
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.angle (angle_s[CORDIC_DW:1]),
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.angle (angle_s[CORDIC_DW:1]),
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.sine (sine_s),
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.sine (sine_s),
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.cosine (),
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.ddata_in (1'b0),
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.ddata_in (1'b0),
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.ddata_out ());
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.ddata_out ());
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@ -39,11 +39,14 @@ module ad_dds_cordic_pipe#(
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// parameters
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// parameters
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// Range = N/A
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parameter DW = 16,
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parameter DW = 16,
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// Range = N/A
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parameter DELAY_DW = 1,
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parameter DELAY_DW = 1,
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// Range = 0-(DW - 1)
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parameter SHIFT = 0) (
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parameter SHIFT = 0) (
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// interface
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// Interface
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input clk,
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input clk,
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(* keep = "TRUE" *) input dir,
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(* keep = "TRUE" *) input dir,
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@ -59,33 +62,34 @@ module ad_dds_cordic_pipe#(
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output signed [ DW-1:0] sgn_shift_x,
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output signed [ DW-1:0] sgn_shift_x,
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output signed [ DW-1:0] sgn_shift_y,
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output signed [ DW-1:0] sgn_shift_y,
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input [DELAY_DW:1] data_delay_in,
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input [DELAY_DW:1] data_delay_in,
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output [DELAY_DW:1] data_delay_out
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output [DELAY_DW:1] data_delay_out);
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);
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// internal registers
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// Registers Declarations
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reg [DELAY_DW:1] data_delay = 'd0;
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reg [DELAY_DW:1] data_delay = 'd0;
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// Wires Declarations
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wire dir_inv = ~dir;
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wire dir_inv = ~dir;
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// stage rotation
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// Stage rotation
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always @(posedge clk)
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always @(posedge clk) begin
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begin
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result_x <= dataa_x + ({DW{dir_inv}} ^ datab_y) + dir_inv;
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result_x <= dataa_x + ({DW{dir_inv}} ^ datab_y) + dir_inv;
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result_y <= dataa_y + ({DW{dir}} ^ datab_x) + dir;
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result_y <= dataa_y + ({DW{dir}} ^ datab_x) + dir;
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result_z <= dataa_z + ({DW{dir_inv}} ^ datab_z) + dir_inv;
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result_z <= dataa_z + ({DW{dir_inv}} ^ datab_z) + dir_inv;
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end
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end
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// stage shift
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// Stage shift
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assign sgn_shift_x = result_x >>> SHIFT + 1;
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assign sgn_shift_x = {{SHIFT{result_x[DW-1]}}, result_x[DW-1:SHIFT]};
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assign sgn_shift_y = result_y >>> SHIFT + 1;
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assign sgn_shift_y = {{SHIFT{result_y[DW-1]}}, result_y[DW-1:SHIFT]};
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// Delay data (if used)
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generate
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generate
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if (DELAY_DW > 1) begin
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if (DELAY_DW > 1) begin
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always @(posedge clk)
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always @(posedge clk) begin
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begin
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data_delay <= data_delay_in;
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data_delay <= data_delay_in;
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end
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end
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end
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end
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@ -37,32 +37,35 @@
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module ad_dds_sine_cordic #(
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module ad_dds_sine_cordic #(
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// parameters
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// Range = 14, 16, 18 and 20
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parameter CORDIC_DW = 16,
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parameter CORDIC_DW = 16,
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parameter DELAY_DW = 1) (
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// Range = N/A
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parameter DELAY_DW = 1) (
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// interface
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// interface
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input clk,
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input clk,
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input [CORDIC_DW-1:0] angle,
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input [CORDIC_DW-1:0] angle,
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output reg [CORDIC_DW-1:0] sine,
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output reg [CORDIC_DW-1:0] sine,
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output reg [CORDIC_DW-1:0] cosine,
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input [ DELAY_DW-1:0] ddata_in,
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input [ DELAY_DW-1:0] ddata_in,
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output reg [ DELAY_DW-1:0] ddata_out);
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output reg [ DELAY_DW-1:0] ddata_out);
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// Local Parameters
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// 1.647 = gain of the system
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// 1.647 = gain of the system
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localparam [19:0] X_VALUE_20 = 318327; // ((20^2)/2)/1.647
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localparam [19:0] X_VALUE_20 = 318327; // ((20^2)/2)/1.647
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localparam [17:0] X_VALUE_18 = 79582; // ((18^2)/2)/1.647
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localparam [17:0] X_VALUE_18 = 79582; // ((18^2)/2)/1.647
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localparam [15:0] X_VALUE_16 = 19883; // ((16^2)/2)/1.647
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localparam [15:0] X_VALUE_16 = 19883; // ((16^2)/2)/1.647
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localparam [13:0] X_VALUE_14 = 4970; // ((14^2)/2)/1.647
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localparam [13:0] X_VALUE_14 = 4970; // ((14^2)/2)/1.647
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// internal registers
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// Registers Declarations
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reg signed [CORDIC_DW-1:0] x0 = 'd0;
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reg signed [CORDIC_DW-1:0] x0 = 'd0;
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reg signed [CORDIC_DW-1:0] y0 = 'd0;
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reg signed [CORDIC_DW-1:0] y0 = 'd0;
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reg signed [CORDIC_DW-1:0] z0 = 'd0;
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reg signed [CORDIC_DW-1:0] z0 = 'd0;
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// internal signals
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// Wires Declarations
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wire [CORDIC_DW-1:0] x_value;
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wire [CORDIC_DW-1:0] x_value;
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wire signed [CORDIC_DW-1:0] x_s [0:CORDIC_DW-1];
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wire signed [CORDIC_DW-1:0] x_s [0:CORDIC_DW-1];
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@ -157,31 +160,26 @@ module ad_dds_sine_cordic #(
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// first two bits represent the quadrant in the unit circle
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// first two bits represent the quadrant in the unit circle
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assign quadrant = angle[CORDIC_DW-1:CORDIC_DW-2];
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assign quadrant = angle[CORDIC_DW-1:CORDIC_DW-2];
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always @(posedge clk)
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always @(posedge clk) begin
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begin
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case (quadrant)
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case (quadrant)
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2'b00,
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2'b00,
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2'b11:
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2'b11: begin
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begin
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x0 <= x_value;
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x0 <= x_value;
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y0 <= 0;
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y0 <= 0;
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z0 <= angle;
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z0 <= angle;
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end
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end
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2'b01:
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2'b01: begin
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begin
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x0 <= 0;
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x0 <= 0;
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y0 <= x_value;
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y0 <= x_value;
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z0 <= {2'b00, angle[CORDIC_DW-3:0]};
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z0 <= {2'b00, angle[CORDIC_DW-3:0]};
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end
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end
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2'b10:
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2'b10: begin
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begin
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x0 <= 0;
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x0 <= 0;
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y0 <= -x_value;
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y0 <= -x_value;
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z0 <= {2'b11, angle[CORDIC_DW-3:0]};
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z0 <= {2'b11 ,angle[CORDIC_DW-3:0]};
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end
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end
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endcase
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endcase
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end
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end
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@ -227,6 +225,7 @@ module ad_dds_sine_cordic #(
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always @(posedge clk) begin
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always @(posedge clk) begin
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ddata_out <= data_in_d[CORDIC_DW-1];
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ddata_out <= data_in_d[CORDIC_DW-1];
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sine <= y_s[CORDIC_DW-1];
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sine <= y_s[CORDIC_DW-1];
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cosine <= x_s[CORDIC_DW-1];
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end
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end
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endmodule
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endmodule
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