axi_dacfifo: Fix axi_dlast generation
The axi_dlast should be asserted max one data beat cycle.main
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2ac096cc3b
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a9543bdf2c
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@ -175,7 +175,7 @@ module axi_dacfifo_rd #(
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assign axi_last_beats_s = {1'b0, axi_last_beats} - 1;
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assign axi_last_beats_s = {1'b0, axi_last_beats} - 1;
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assign axi_dvalid_s = ((axi_last_beats_cntr > axi_last_beats_s) && (axi_araddr_prev == axi_last_raddr)) ? 0 : axi_rvalid & axi_rready;
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assign axi_dvalid_s = ((axi_last_beats_cntr > axi_last_beats_s) && (axi_araddr_prev == axi_last_raddr)) ? 0 : axi_rvalid & axi_rready;
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assign axi_dlast_s = (axi_araddr_prev == axi_last_raddr) ? 1 : 0;
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assign axi_dlast_s = (axi_araddr == axi_last_raddr) ? 1 : 0;
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always @(posedge axi_clk) begin
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always @(posedge axi_clk) begin
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if (axi_resetn == 1'b0) begin
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if (axi_resetn == 1'b0) begin
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@ -185,7 +185,7 @@ module axi_dacfifo_rd #(
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end else begin
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end else begin
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axi_ddata <= axi_rdata;
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axi_ddata <= axi_rdata;
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axi_dvalid <= axi_dvalid_s;
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axi_dvalid <= axi_dvalid_s;
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axi_dlast <= axi_dlast_s;
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axi_dlast <= axi_dlast_s & axi_rlast;
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if (axi_xfer_req == 1'b1) begin
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if (axi_xfer_req == 1'b1) begin
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axi_rready <= axi_rvalid;
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axi_rready <= axi_rvalid;
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end
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end
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