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ad_quadmxfe1_ebz/vcu118/system_project.tcl: Update comments 

Update PLL selection docs.
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Laszlo Nagy 2022-06-08 15:26:14 +03:00
parent 6525a37375
commit a8174ac038
1 changed files with 6 additions and 1 deletions
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projects/ad_quadmxfe1_ebz/vcu118/system_project.tcl
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@ -22,6 +22,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode
# [RX/TX]_PLL_SEL : used in 64B66B mode,
# 0 - CPLL for lane rates 4-12.5 Gbps and integer sub-multiples
# 1 - QPLL0 for lane rates 19.6–32.75 Gbps and integer sub-multiples (e.g. 9.8–16.375;)
# 2 - QPLL1 for lane rates 16.0–26.0 Gbps and integer sub-multiple (e.g. 8.0–13.0;)
# For detail see JESD204 PHY v4.0 pg198-jesd204-phy.pdf and ug578-ultrascale-gty-transceivers.pdf
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link