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util_dacfifo: General clean up of the IO, input/output data has the same width

main
Istvan Csomortani 2015-05-06 16:32:44 +03:00
parent 0613dca0b7
commit a7c96fdac8
1 changed files with 71 additions and 222 deletions
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library/util_dacfifo/util_dacfifo.v
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@ -41,262 +41,111 @@
module util_dacfifo ( module util_dacfifo (
// DMA interface
// FIFO read interface dma_clk,
rd_fifo_clk, // should be connected to a lower system clock dma_rst,
rd_fifo_rst, dma_valid,
rd_fifo_en, dma_data,
rd_fifo_valid, dma_ready,
rd_fifo_data, dma_xfer_req,
rd_fifo_underflow, dma_xfer_last,
rd_fifo_xfer_req,
// AXIS Slave interface (connection with DMAC) // DAC interface
s_axis_aclk, dac_clk,
s_axis_aresetn, dac_valid,
s_axis_ready, dac_data
s_axis_valid,
s_axis_data,
s_axis_last,
// FIFO write interface (connection with upack/DAC)
wr_fifo_clk, // should be connected to the dac clock
wr_fifo_valid,
wr_fifo_sync,
wr_fifo_data
); );
// parameters
parameter RD_INTERFACE_MODE = 0;
// depth of the FIFO // depth of the FIFO
parameter FIFO_WADDR_WIDTH = 6; parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 128;
// read/write interface data width
parameter FIFO_RDATA_WIDTH = 64; // should be less or equal to FIFO_WDATA_WIDTH
parameter FIFO_WDATA_WIDTH = 128;
// local parameters // local parameters
// supported ratios with the write interface are 1:1, 1:2, 1:4, 1:8
localparam IF_RATIO = FIFO_WDATA_WIDTH/FIFO_RDATA_WIDTH;
// FSM state definitions
localparam IDLE = 0;
localparam READ = 1;
// interface type definitions
localparam RD_FIFO_IF = 0;
localparam S_AXIS_IF = 1;
// port definitions // port definitions
// RD FIFO interface // DMA interface
input rd_fifo_clk;
input rd_fifo_rst;
output rd_fifo_en;
input rd_fifo_valid;
input [(FIFO_RDATA_WIDTH-1):0] rd_fifo_data;
input rd_fifo_underflow;
input rd_fifo_xfer_req;
// Slave AXI Stream interface input dma_clk;
input s_axis_aclk; input dma_rst;
input s_axis_aresetn; input dma_valid;
input s_axis_valid; input [(DATA_WIDTH-1):0] dma_data;
input [(FIFO_RDATA_WIDTH-1):0] s_axis_data; output dma_ready;
input s_axis_last; input dma_xfer_req;
output s_axis_ready; input dma_xfer_last;
// WR FIFO interface // DAC interface
input wr_fifo_clk;
input wr_fifo_valid; input dac_clk;
input wr_fifo_sync; input dac_valid;
output [(FIFO_WDATA_WIDTH-1):0] wr_fifo_data; output [(DATA_WIDTH-1):0] dac_data;
// internal registers // internal registers
reg [FIFO_WADDR_WIDTH-1:0] fifo_waddr = 'h0; reg [(ADDR_WIDTH-1):0] dma_waddr = 'b0;
reg [(FIFO_RDATA_WIDTH*IF_RATIO)-1:0] fifo_rdata = 'h0; reg [(ADDR_WIDTH-1):0] dma_lastaddr = 'b0;
reg dma_xfer_req_ff = 1'b0;
reg dma_ready = 1'b0;
reg [FIFO_WDATA_WIDTH-1:0] wr_fifo_data = 'h0; reg [(ADDR_WIDTH-1):0] dac_raddr = 'b0;
reg rd_en = 1'b0; reg [(DATA_WIDTH-1):0] dac_data = 'b0;
reg fifo_ren = 1'b0;
reg [FIFO_WADDR_WIDTH-1:0] fifo_maxraddr = {FIFO_WADDR_WIDTH{1'b1}};
reg [FIFO_WADDR_WIDTH-1:0] fifo_raddr = 'h0;
reg [FIFO_WADDR_WIDTH-1:0] fifo_raddr_ff = 'h0;
reg [ 2:0] fifo_rdata_count = 3'h0;
reg fifo_state = IDLE;
reg fifo_next_state = IDLE;
// internal wires // internal wires
wire dma_wren;
wire [(DATA_WIDTH-1):0] dac_data_s;
// common read interface // write interface
wire rd_clk; always @(posedge dma_clk) begin
wire rd_rst; if(dma_rst == 1'b1) begin
wire rd_ready; // or could be rd_en dma_ready <= 1'b0;
wire [FIFO_RDATA_WIDTH-1:0] rd_data; dma_xfer_req_ff <= 1'b0;
wire rd_valid;
wire [FIFO_WDATA_WIDTH-1:0] fifo_wdata_s;
// define the common read interface
generate if (RD_INTERFACE_MODE == RD_FIFO_IF) begin
assign rd_clk = rd_fifo_clk;
assign rd_rst = rd_fifo_rst;
assign rd_data = rd_fifo_data;
assign rd_valid = rd_fifo_valid;
assign rd_fifo_en = rd_ready;
end else begin // if (RD_INTERFACE_MODE == S_AXIS_IF)
assign rd_clk = s_axis_aclk;
assign rd_rst = ~s_axis_aresetn;
assign rd_data = s_axis_data;
assign rd_valid = s_axis_valid;
assign s_axis_ready = rd_ready;
end
endgenerate
// **** Define FIFO state machine ****
// in <IDLE> the FIFO writes data into DAC
// in <READ> the FIFO is loaded with data through the S_AXIS interface,
// the FIFO write interface sending NULLs to the DAC during the read process
always @(posedge rd_clk) begin
if(rd_rst == 1) begin
fifo_state <= IDLE;
end else begin end else begin
fifo_state <= fifo_next_state; dma_ready <= 1'b1; // Fifo is always ready
end dma_xfer_req_ff <= dma_xfer_req;
end
// next state logic
generate if (RD_INTERFACE_MODE == RD_FIFO_IF) begin
always @(rd_valid or rd_fifo_xfer_req) begin
case (fifo_state)
IDLE: begin
if((rd_valid == 1) && (rd_fifo_xfer_req == 1))
fifo_next_state <= READ;
end
READ: begin
if(rd_fifo_xfer_req == 0)
fifo_next_state <= IDLE;
end
endcase
end
end else begin // if (RD_INTERFACE_MODE == S_AXIS_IF)
always @(rd_valid or s_axis_last) begin
case (fifo_state)
IDLE: begin
if(rd_valid == 1)
fifo_next_state <= READ;
end
READ: begin
if((rd_valid == 1) && (s_axis_last == 1))
fifo_next_state <= IDLE;
end
endcase
end
end
endgenerate
// FIFO is always ready to accept data from memory
assign rd_ready = 1;
// adjust the RD data width to the WR data width
generate if (IF_RATIO > 1) begin
always @(posedge rd_clk) begin
if(s_axis_valid == 1) begin
fifo_rdata <= {s_axis_data, fifo_rdata[((IF_RATIO * FIFO_RDATA_WIDTH)-1):FIFO_RDATA_WIDTH]};
fifo_rdata_count <= (fifo_rdata_count < (IF_RATIO - 1)) ? (fifo_rdata_count + 1) : 3'h0;
end end
end end
always @(posedge dma_clk) begin
if(dma_rst == 1'b1) begin
dma_waddr <= 'b0;
dma_lastaddr <= {ADDR_WIDTH{1'b1}};
end else begin end else begin
if (dma_valid && dma_xfer_req) begin
always @(posedge rd_clk) begin dma_waddr <= dma_waddr + 1;
if(s_axis_valid == 1) begin
fifo_rdata <= s_axis_data;
end end
fifo_rdata_count <= 3'b0; if (dma_xfer_last) begin
dma_lastaddr <= dma_waddr;
dma_waddr <= 'b0;
end end
end
endgenerate
// generate address for the incoming data
always @(posedge rd_clk) begin
if(fifo_state == IDLE) begin
fifo_raddr <= 'b0;
end else begin
fifo_raddr <= (fifo_ren == 1) ? (fifo_raddr + 1) : fifo_raddr;
end
fifo_raddr_ff <= fifo_raddr;
end
// save the last valid address
generate if (RD_INTERFACE_MODE == RD_FIFO_IF) begin
always @(posedge rd_clk) begin
if(rd_fifo_xfer_req == 0) begin
fifo_maxraddr <= fifo_raddr;
end end
end end
end else begin // if (RD_INTERFACE_MODE == S_AXIS_IF) assign dma_wren = dma_valid & dma_xfer_req;
always @(posedge rd_clk) begin // read interface
if((rd_valid == 1) && (s_axis_last == 1)) begin always @(posedge dac_clk) begin
fifo_maxraddr <= fifo_raddr; if(dac_valid == 1'b1) begin
dac_raddr <= (dac_raddr < dma_lastaddr) ? (dac_raddr + 1) : 'b0;
end end
dac_data <= dac_data_s;
end end
end
endgenerate
// generate wren for the incoming data
always @(posedge rd_clk) begin
fifo_ren <= (fifo_rdata_count == (IF_RATIO - 1)) ? rd_valid : 1'b0;
end
// write interface, FIFO writes data to DAC when its state is IDLE
always @(posedge wr_fifo_clk) begin
if(fifo_state == IDLE) begin
fifo_waddr <= (fifo_waddr < fifo_maxraddr) ? (fifo_waddr + 1) : 'b0;
end else begin
fifo_waddr <= 'b0;
end
wr_fifo_data <= fifo_wdata_s;
end
// memory instantiation // memory instantiation
ad_mem #( ad_mem #(
.ADDR_WIDTH (FIFO_WADDR_WIDTH), .ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (FIFO_WDATA_WIDTH)) .DATA_WIDTH (DATA_WIDTH))
i_mem_fifo ( i_mem_fifo (
.clka (rd_clk), .clka (dma_clk),
.wea (fifo_ren), .wea (dma_wren),
.addra (fifo_raddr_ff), .addra (dma_waddr),
.dina (fifo_rdata), .dina (dma_data),
.clkb (wr_fifo_clk), .clkb (dac_clk),
.addrb (fifo_waddr), .addrb (dac_raddr),
.doutb (fifo_wdata_s)); .doutb (dac_data_s));
endmodule endmodule