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axi_ad9361: tx_valid must be controlled by the TDD controller

main
Istvan Csomortani 2016-02-12 14:33:34 +02:00
parent e381d5170c
commit a747fad540
2 changed files with 11 additions and 1 deletions
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5
library/axi_ad9361/axi_ad9361.v
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@ -301,6 +301,7 @@ module axi_ad9361 (
wire [47:0] adc_data_s; wire [47:0] adc_data_s;
wire adc_status_s; wire adc_status_s;
wire dac_valid_s; wire dac_valid_s;
wire g_dac_valid_s;
wire [47:0] dac_data_s; wire [47:0] dac_data_s;
wire dac_valid_i0_s; wire dac_valid_i0_s;
wire dac_valid_q0_s; wire dac_valid_q0_s;
@ -390,7 +391,7 @@ module axi_ad9361 (
.adc_status (adc_status_s), .adc_status (adc_status_s),
.adc_r1_mode (adc_r1_mode), .adc_r1_mode (adc_r1_mode),
.adc_ddr_edgesel (adc_ddr_edgesel), .adc_ddr_edgesel (adc_ddr_edgesel),
.dac_valid (dac_valid_s), .dac_valid (g_dac_valid_s),
.dac_data (dac_data_s), .dac_data (dac_data_s),
.dac_r1_mode (dac_r1_mode), .dac_r1_mode (dac_r1_mode),
.tdd_enable (tdd_enable_s), .tdd_enable (tdd_enable_s),
@ -443,10 +444,12 @@ module axi_ad9361 (
.tdd_status (tdd_status_s), .tdd_status (tdd_status_s),
.tdd_sync (tdd_sync), .tdd_sync (tdd_sync),
.tdd_sync_cntr (tdd_sync_cntr), .tdd_sync_cntr (tdd_sync_cntr),
.tx_valid (dac_valid_s),
.tx_valid_i0 (dac_valid_i0_s), .tx_valid_i0 (dac_valid_i0_s),
.tx_valid_q0 (dac_valid_q0_s), .tx_valid_q0 (dac_valid_q0_s),
.tx_valid_i1 (dac_valid_i1_s), .tx_valid_i1 (dac_valid_i1_s),
.tx_valid_q1 (dac_valid_q1_s), .tx_valid_q1 (dac_valid_q1_s),
.tdd_tx_valid (g_dac_valid_s),
.tdd_tx_valid_i0 (dac_valid_i0), .tdd_tx_valid_i0 (dac_valid_i0),
.tdd_tx_valid_q0 (dac_valid_q0), .tdd_tx_valid_q0 (dac_valid_q0),
.tdd_tx_valid_i1 (dac_valid_i1), .tdd_tx_valid_i1 (dac_valid_i1),

7
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -65,11 +65,13 @@ module axi_ad9361_tdd (
// tx/rx data flow control // tx/rx data flow control
tx_valid,
tx_valid_i0, tx_valid_i0,
tx_valid_q0, tx_valid_q0,
tx_valid_i1, tx_valid_i1,
tx_valid_q1, tx_valid_q1,
tdd_tx_valid,
tdd_tx_valid_i0, tdd_tx_valid_i0,
tdd_tx_valid_q0, tdd_tx_valid_q0,
tdd_tx_valid_i1, tdd_tx_valid_i1,
@ -119,11 +121,13 @@ module axi_ad9361_tdd (
// tx data flow control // tx data flow control
input tx_valid;
input tx_valid_i0; input tx_valid_i0;
input tx_valid_q0; input tx_valid_q0;
input tx_valid_i1; input tx_valid_i1;
input tx_valid_q1; input tx_valid_q1;
output tdd_tx_valid;
output tdd_tx_valid_i0; output tdd_tx_valid_i0;
output tdd_tx_valid_q0; output tdd_tx_valid_q0;
output tdd_tx_valid_i1; output tdd_tx_valid_i1;
@ -158,6 +162,7 @@ module axi_ad9361_tdd (
reg tdd_slave_synced = 1'b0; reg tdd_slave_synced = 1'b0;
reg tdd_tx_valid = 1'b0;
reg tdd_tx_valid_i0 = 1'b0; reg tdd_tx_valid_i0 = 1'b0;
reg tdd_tx_valid_q0 = 1'b0; reg tdd_tx_valid_q0 = 1'b0;
reg tdd_tx_valid_i1 = 1'b0; reg tdd_tx_valid_i1 = 1'b0;
@ -216,11 +221,13 @@ module axi_ad9361_tdd (
always @(posedge clk) begin always @(posedge clk) begin
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
tdd_tx_valid <= tx_valid & tdd_tx_dp_en_s;
tdd_tx_valid_i0 <= tx_valid_i0 & tdd_tx_dp_en_s; tdd_tx_valid_i0 <= tx_valid_i0 & tdd_tx_dp_en_s;
tdd_tx_valid_q0 <= tx_valid_q0 & tdd_tx_dp_en_s; tdd_tx_valid_q0 <= tx_valid_q0 & tdd_tx_dp_en_s;
tdd_tx_valid_i1 <= tx_valid_i1 & tdd_tx_dp_en_s; tdd_tx_valid_i1 <= tx_valid_i1 & tdd_tx_dp_en_s;
tdd_tx_valid_q1 <= tx_valid_q1 & tdd_tx_dp_en_s; tdd_tx_valid_q1 <= tx_valid_q1 & tdd_tx_dp_en_s;
end else begin end else begin
tdd_tx_valid <= tx_valid;
tdd_tx_valid_i0 <= tx_valid_i0; tdd_tx_valid_i0 <= tx_valid_i0;
tdd_tx_valid_q0 <= tx_valid_q0; tdd_tx_valid_q0 <= tx_valid_q0;
tdd_tx_valid_i1 <= tx_valid_i1; tdd_tx_valid_i1 <= tx_valid_i1;