From a6e6b3f96e4fed4f55dcc559ea76d41ada0d789e Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 29 Aug 2016 15:59:15 +0300 Subject: [PATCH] version_upgrade: Update fmcomms1 common design to Vivado 2016.2 --- projects/fmcomms1/common/fmcomms1_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 826ecaaf8..2e3eef67a 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -68,7 +68,7 @@ # reference clock - set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 refclk_clkgen] + set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 refclk_clkgen] set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {30} ] $refclk_clkgen set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} ] $refclk_clkgen set_property -dict [list CONFIG.JITTER_SEL {Min_O_Jitter} ] $refclk_clkgen