From 656246f2baaaa5265c2b8e647da33fad04b3a8ac Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 17 Dec 2014 16:16:01 +0200 Subject: [PATCH 01/22] fmcomms2: Updated VC707 project to fix ethernet problem --- projects/fmcomms2/vc707/system_project.tcl | 3 +++ projects/fmcomms2/vc707/system_top.v | 1 + 2 files changed, 4 insertions(+) diff --git a/projects/fmcomms2/vc707/system_project.tcl b/projects/fmcomms2/vc707/system_project.tcl index b7bff3f85..6e56ee0b9 100644 --- a/projects/fmcomms2/vc707/system_project.tcl +++ b/projects/fmcomms2/vc707/system_project.tcl @@ -11,6 +11,9 @@ adi_project_files fmcomms2_vc707 [list \ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + adi_project_run fmcomms2_vc707 diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v index 5d2c7b9b4..4058a3237 100644 --- a/projects/fmcomms2/vc707/system_top.v +++ b/projects/fmcomms2/vc707/system_top.v @@ -303,6 +303,7 @@ module system_top ( .mgt_clk_clk_n (mgt_clk_n), .mgt_clk_clk_p (mgt_clk_p), .phy_rstn (phy_rstn), + .phy_sd (1'b1), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), From 1a9eb8196a8391767f3417babc27f6f78f577ae7 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 18 Dec 2014 17:49:00 +0200 Subject: [PATCH 02/22] VC707: Fixed linear flash timings --- projects/common/vc707/vc707_system_bd.tcl | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index ed364cf03..e413fd4ef 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -162,7 +162,21 @@ set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dm # linear flash set axi_linear_flash [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_emc:3.0 axi_linear_flash] -set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.EMC_BOARD_INTERFACE {linear_flash}] $axi_linear_flash +#set_property -dict [ list CONFIG.C_MEM0_TYPE {2} CONFIG.C_S_AXI_MEM_ID_WIDTH {0} CONFIG.C_TAVDV_PS_MEM_0 {96000} CONFIG.C_TCEDV_PS_MEM_0 {96000} CONFIG.C_THZCE_PS_MEM_0 {7000} CONFIG.C_TLZWE_PS_MEM_0 {0} CONFIG.C_TPACC_PS_FLASH_0 {15000} CONFIG.C_TWC_PS_MEM_0 {15000} CONFIG.C_TWPH_PS_MEM_0 {20000} CONFIG.C_TWP_PS_MEM_0 {40000} CONFIG.C_WR_REC_TIME_MEM_0 {0} CONFIG.EMC_BOARD_INTERFACE {linear_flash} CONFIG.USE_BOARD_FLOW {true} ] $axi_linear_flash + +set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_linear_flash +set_property -dict [list CONFIG.EMC_BOARD_INTERFACE {linear_flash}] $axi_linear_flash +set_property -dict [list CONFIG.C_MEM0_TYPE {2}] $axi_linear_flash +set_property -dict [list CONFIG.C_S_AXI_MEM_ID_WIDTH {0}] $axi_linear_flash +set_property -dict [list CONFIG.C_THZCE_PS_MEM_0 {7000}] $axi_linear_flash +set_property -dict [list CONFIG.C_TLZWE_PS_MEM_0 {0}] $axi_linear_flash +set_property -dict [list CONFIG.C_TWC_PS_MEM_0 {15000}] $axi_linear_flash +set_property -dict [list CONFIG.C_WR_REC_TIME_MEM_0 {0}] $axi_linear_flash +set_property -dict [list CONFIG.C_TWP_PS_MEM_0 {40000}] $axi_linear_flash +set_property -dict [list CONFIG.C_TWPH_PS_MEM_0 {20000}] $axi_linear_flash +set_property -dict [list CONFIG.C_TPACC_PS_FLASH_0 {15000}] $axi_linear_flash +set_property -dict [list CONFIG.C_TCEDV_PS_MEM_0 {96000}] $axi_linear_flash +set_property -dict [list CONFIG.C_TAVDV_PS_MEM_0 {96000}] $axi_linear_flash set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 sys_const_vcc] From 758ac6bb8ef2cc83a5175ca7a7e8d83fff7111f9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 12:58:44 -0500 Subject: [PATCH 03/22] plddr3: sys-rst from board pushbutton --- projects/common/zc706/zc706_system_constr.xdc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/projects/common/zc706/zc706_system_constr.xdc b/projects/common/zc706/zc706_system_constr.xdc index b37708619..b24b7baa9 100644 --- a/projects/common/zc706/zc706_system_constr.xdc +++ b/projects/common/zc706/zc706_system_constr.xdc @@ -1,5 +1,8 @@ # constraints + +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS15} [get_ports sys_rst] + # hdmi set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk] From daba3fb72e9970b219b0d9f53cb0b2510608bde1 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 12:58:54 -0500 Subject: [PATCH 04/22] plddr3: sys-rst from board pushbutton --- projects/common/zc706/zc706_system_plddr3.tcl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/projects/common/zc706/zc706_system_plddr3.tcl b/projects/common/zc706/zc706_system_plddr3.tcl index cd1b2b87e..cf3793a09 100644 --- a/projects/common/zc706/zc706_system_plddr3.tcl +++ b/projects/common/zc706/zc706_system_plddr3.tcl @@ -14,6 +14,7 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { set m_instance [create_bd_cell -type hier $m_name] current_bd_instance $m_instance + create_bd_pin -dir I -type rst sys_rst create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk @@ -68,7 +69,8 @@ proc p_plddr3_fifo {p_name m_name adc_data_width} { connect_bd_net -net axi_clk [get_bd_pins axi_ddr_cntrl/ui_clk] [get_bd_pins axi_fifo2s/axi_clk] connect_bd_net -net adc_rst [get_bd_pins axi_rstgen/ext_reset_in] - connect_bd_net -net adc_rst [get_bd_pins axi_ddr_cntrl/sys_rst] + connect_bd_net -net sys_rst [get_bd_pins sys_rst] + connect_bd_net -net sys_rst [get_bd_pins axi_ddr_cntrl/sys_rst] connect_bd_net -net axi_clk [get_bd_pins axi_rstgen/slowest_sync_clk] connect_bd_net -net axi_resetn [get_bd_pins axi_rstgen/peripheral_aresetn] connect_bd_net -net axi_resetn [get_bd_pins axi_fifo2s/axi_resetn] From 51bdcb1b123f206fe15987f5ac83ad1e0d3da076 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 12:59:04 -0500 Subject: [PATCH 05/22] plddr3: sys-rst from board pushbutton --- projects/daq2/zc706/system_bd.tcl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl index cc2ef3898..e93774c1d 100644 --- a/projects/daq2/zc706/system_bd.tcl +++ b/projects/daq2/zc706/system_bd.tcl @@ -4,8 +4,11 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 +create_bd_port -dir I -type rst sys_rst +set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9680_fifo/sys_rst] connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk] create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] \ From 0cc29fe03bb6b33a7dfb8aebba615feb76ca90a2 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 12:59:16 -0500 Subject: [PATCH 06/22] plddr3: sys-rst from board pushbutton --- projects/daq2/zc706/system_top.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v index 14b535aa5..c789096e5 100644 --- a/projects/daq2/zc706/system_top.v +++ b/projects/daq2/zc706/system_top.v @@ -41,6 +41,7 @@ module system_top ( + sys_rst, sys_clk_p, sys_clk_n, @@ -555,6 +556,7 @@ module system_top ( .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), .tx_data_n (tx_data_n), .tx_data_p (tx_data_p), .tx_ref_clk (tx_ref_clk), From 33a8c8a1552166e5215624790b8d9f966b223674 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 12:59:25 -0500 Subject: [PATCH 07/22] plddr3: sys-rst from board pushbutton --- projects/fmcadc4/zc706/system_bd.tcl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 06d15fdab..df43f763b 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -4,8 +4,11 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl p_plddr3_fifo [current_bd_instance .] axi_ad9234_fifo 256 +create_bd_port -dir I -type rst sys_rst +set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9234_fifo/sys_rst] connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9234_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9234_fifo/sys_clk] create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9234_fifo/axi_fifo2s/axi] \ From ad144ef06a8623e16a7bc3a5a5ea348051de7450 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 12:59:36 -0500 Subject: [PATCH 08/22] plddr3: sys-rst from board pushbutton --- projects/fmcadc4/zc706/system_top.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/projects/fmcadc4/zc706/system_top.v b/projects/fmcadc4/zc706/system_top.v index 8496a20ef..eb35c5767 100644 --- a/projects/fmcadc4/zc706/system_top.v +++ b/projects/fmcadc4/zc706/system_top.v @@ -41,6 +41,7 @@ module system_top ( + sys_rst, sys_clk_p, sys_clk_n, @@ -124,6 +125,7 @@ module system_top ( spi_clk, spi_sdio); + input sys_rst; input sys_clk_p; input sys_clk_n; @@ -550,7 +552,8 @@ module system_top ( .spi_sdo_i (spi_mosi), .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p)); + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst)); endmodule From f4774d6f98835db5f315012d6bd204596ab8a34c Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 13:00:13 -0500 Subject: [PATCH 09/22] fifo2s: false path typo on source signals --- library/axi_fifo2s/axi_fifo2s_constr.xdc | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/library/axi_fifo2s/axi_fifo2s_constr.xdc b/library/axi_fifo2s/axi_fifo2s_constr.xdc index e7ba7f13f..9e54c6a6c 100644 --- a/library/axi_fifo2s/axi_fifo2s_constr.xdc +++ b/library/axi_fifo2s/axi_fifo2s_constr.xdc @@ -1,13 +1,16 @@ -set_false_path -from [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ +set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] -set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ +set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ -to [get_cells *dma_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] -set_false_path -from [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ +set_false_path -from [get_cells *adc_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ -to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] -set_false_path -from [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ +set_false_path -from [get_cells *axi_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ -to [get_cells *adc_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] - +set_false_path -from [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells *up_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] +set_false_path -from [get_cells *adc_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \ + -to [get_cells *axi_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] From 153a4cef180e53fc2918c0a71a2356022a2dfc78 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 15 Dec 2014 14:39:40 -0500 Subject: [PATCH 10/22] daq2: missing sys_rst decl. --- projects/daq2/zc706/system_top.v | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v index c789096e5..999f6866f 100644 --- a/projects/daq2/zc706/system_top.v +++ b/projects/daq2/zc706/system_top.v @@ -135,6 +135,7 @@ module system_top ( spi_sdio, spi_dir); + input sys_rst; input sys_clk_p; input sys_clk_n; From c3529f112ff016f183a2fc24a4583e35e5c8853e Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 16 Dec 2014 08:48:13 -0500 Subject: [PATCH 11/22] up_gt: move status to up clock --- library/common/up_gt.v | 60 ++++++++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 14 deletions(-) diff --git a/library/common/up_gt.v b/library/common/up_gt.v index 7f75b41a8..95d3dbaab 100644 --- a/library/common/up_gt.v +++ b/library/common/up_gt.v @@ -285,6 +285,14 @@ module up_gt ( reg up_es_dmaerr = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; + reg [ 7:0] up_rx_rst_done_m1 = 'd0; + reg [ 7:0] up_rx_pll_locked_m1 = 'd0; + reg [ 7:0] up_tx_rst_done_m1 = 'd0; + reg [ 7:0] up_tx_pll_locked_m1 = 'd0; + reg [ 7:0] up_rx_rst_done = 'd0; + reg [ 7:0] up_rx_pll_locked = 'd0; + reg [ 7:0] up_tx_rst_done = 'd0; + reg [ 7:0] up_tx_pll_locked = 'd0; reg rx_sysref_m1 = 'd0; reg rx_sysref_m2 = 'd0; reg rx_sysref_m3 = 'd0; @@ -322,10 +330,10 @@ module up_gt ( wire up_wreq_s; wire up_rreq_s; - wire rx_rst_done_s; - wire rx_pll_locked_s; - wire tx_rst_done_s; - wire tx_pll_locked_s; + wire up_rx_rst_done_s; + wire up_rx_pll_locked_s; + wire up_tx_rst_done_s; + wire up_tx_pll_locked_s; wire up_drp_preset_s; wire up_gt_pll_preset_s; wire up_gt_rx_preset_s; @@ -353,20 +361,20 @@ module up_gt ( // status inputs - assign rx_rst_done_s = & rx_rst_done; - assign rx_pll_locked_s = & rx_pll_locked; + assign up_rx_rst_done_s = & up_rx_rst_done; + assign up_rx_pll_locked_s = & up_rx_pll_locked; - assign tx_rst_done_s = & tx_rst_done; - assign tx_pll_locked_s = & tx_pll_locked; + assign up_tx_rst_done_s = & up_tx_rst_done; + assign up_tx_pll_locked_s = & up_tx_pll_locked; // resets assign up_drp_preset_s = ~up_drp_resetn; assign up_gt_pll_preset_s = ~up_gt_pll_resetn; - assign up_gt_rx_preset_s = ~(up_gt_pll_resetn & up_gt_rx_resetn & rx_pll_locked_s); - assign up_gt_tx_preset_s = ~(up_gt_pll_resetn & up_gt_tx_resetn & tx_pll_locked_s); - assign up_rx_preset_s = ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_resetn & rx_pll_locked_s & rx_rst_done_s); - assign up_tx_preset_s = ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_resetn & tx_pll_locked_s & tx_rst_done_s); + assign up_gt_rx_preset_s = ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_pll_locked_s); + assign up_gt_tx_preset_s = ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_pll_locked_s); + assign up_rx_preset_s = ~(up_gt_pll_resetn & up_gt_rx_resetn & up_rx_resetn & up_rx_pll_locked_s & up_rx_rst_done_s); + assign up_tx_preset_s = ~(up_gt_pll_resetn & up_gt_tx_resetn & up_tx_resetn & up_tx_pll_locked_s & up_tx_rst_done_s); // processor write interface @@ -548,13 +556,13 @@ module up_gt ( 8'h0a: up_rdata <= {24'd0, 2'd0, up_rx_sys_clk_sel, 1'd0, up_rx_out_clk_sel}; 8'h0b: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref}; 8'h0c: up_rdata <= {31'd0, up_rx_sync}; - 8'h0d: up_rdata <= {15'd0, up_rx_status, rx_rst_done, rx_pll_locked}; + 8'h0d: up_rdata <= {15'd0, up_rx_status, up_rx_rst_done, up_rx_pll_locked}; 8'h18: up_rdata <= {31'd0, up_gt_tx_resetn}; 8'h19: up_rdata <= {31'd0, up_tx_resetn}; 8'h1a: up_rdata <= {24'd0, 2'd0, up_tx_sys_clk_sel, 1'd0, up_tx_out_clk_sel}; 8'h1b: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref}; 8'h1c: up_rdata <= {31'd0, up_tx_sync}; - 8'h1d: up_rdata <= {15'd0, up_tx_status, tx_rst_done, tx_pll_locked}; + 8'h1d: up_rdata <= {15'd0, up_tx_status, up_tx_rst_done, up_tx_pll_locked}; 8'h23: up_rdata <= {24'd0, up_lanesel}; 8'h24: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; 8'h25: up_rdata <= {15'd0, up_drp_status_s, up_drp_rdata_s}; @@ -589,6 +597,30 @@ module up_gt ( ad_rst i_rx_rst_reg (.preset(up_rx_preset_s), .clk(rx_clk), .rst(rx_rst)); ad_rst i_tx_rst_reg (.preset(up_tx_preset_s), .clk(tx_clk), .rst(tx_rst)); + // reset done & pll locked + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rx_rst_done_m1 <= 'd0; + up_rx_pll_locked_m1 <= 'd0; + up_tx_rst_done_m1 <= 'd0; + up_tx_pll_locked_m1 <= 'd0; + up_rx_rst_done <= 'd0; + up_rx_pll_locked <= 'd0; + up_tx_rst_done <= 'd0; + up_tx_pll_locked <= 'd0; + end else begin + up_rx_rst_done_m1 <= rx_rst_done; + up_rx_pll_locked_m1 <= rx_pll_locked; + up_tx_rst_done_m1 <= tx_rst_done; + up_tx_pll_locked_m1 <= tx_pll_locked; + up_rx_rst_done <= up_rx_rst_done_m1; + up_rx_pll_locked <= up_rx_pll_locked_m1; + up_tx_rst_done <= up_tx_rst_done_m1; + up_tx_pll_locked <= up_tx_pll_locked_m1; + end + end + // rx sysref & sync assign rx_sysref_s = (up_rx_sysref_sel == 1'b1) ? rx_ext_sysref : up_rx_sysref; From a6cf615ee0e1c8faab5344d7c553fb2b6e5b6826 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 17 Dec 2014 19:07:43 +0200 Subject: [PATCH 12/22] zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc --- projects/common/zc706/zc706_system_constr.xdc | 2 -- projects/common/zc706/zc706_system_mig_constr.xdc | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/common/zc706/zc706_system_constr.xdc b/projects/common/zc706/zc706_system_constr.xdc index b24b7baa9..a865efe97 100644 --- a/projects/common/zc706/zc706_system_constr.xdc +++ b/projects/common/zc706/zc706_system_constr.xdc @@ -1,8 +1,6 @@ # constraints -set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS15} [get_ports sys_rst] - # hdmi set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk] diff --git a/projects/common/zc706/zc706_system_mig_constr.xdc b/projects/common/zc706/zc706_system_mig_constr.xdc index 5a8aa9c02..81c249b8a 100644 --- a/projects/common/zc706/zc706_system_mig_constr.xdc +++ b/projects/common/zc706/zc706_system_mig_constr.xdc @@ -6,3 +6,5 @@ set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVDS} [get_ports sys_clk_n] create_clock -name sys_clk -period 5.00 [get_ports sys_clk_p] +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS15} [get_ports sys_rst] + From 7ec1e282d90c5bcf315b02826ba7127cc4834e29 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:00:35 +0200 Subject: [PATCH 13/22] daq2_zc706: Add constraint file for the PLDDR --- projects/daq2/zc706/system_project.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/daq2/zc706/system_project.tcl b/projects/daq2/zc706/system_project.tcl index 3714ab0ab..7cdb71356 100644 --- a/projects/daq2/zc706/system_project.tcl +++ b/projects/daq2/zc706/system_project.tcl @@ -10,6 +10,7 @@ adi_project_files daq2_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] From 8fc1f046a40c3a56bafd7798e088ea9f6a428d13 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:01:16 +0200 Subject: [PATCH 14/22] fmcadc4_zc706: Add constraint file for PLDDR --- projects/fmcadc4/zc706/system_project.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/fmcadc4/zc706/system_project.tcl b/projects/fmcadc4/zc706/system_project.tcl index 32a561fdb..d6e72cff8 100644 --- a/projects/fmcadc4/zc706/system_project.tcl +++ b/projects/fmcadc4/zc706/system_project.tcl @@ -10,6 +10,7 @@ adi_project_files fmcadc4_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] adi_project_run fmcadc4_zc706 From df205f5cea601642780ac0be7678d6e85ce5a4a4 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:04:01 +0200 Subject: [PATCH 15/22] fmcadc2_zc706: Connect PLDDR rst to external push button --- projects/fmcadc2/zc706/system_bd.tcl | 3 +++ projects/fmcadc2/zc706/system_top.v | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl index 104997d4d..a4b798126 100644 --- a/projects/fmcadc2/zc706/system_bd.tcl +++ b/projects/fmcadc2/zc706/system_bd.tcl @@ -4,8 +4,11 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl p_plddr3_fifo [current_bd_instance .] axi_ad9625_fifo 256 +create_bd_port -dir I -type rst sys_rst +set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9680_fifo/sys_rst] connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9625_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9625_fifo/sys_clk] create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_fifo/axi_fifo2s/axi] \ diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v index c9beac654..9b9ae294b 100644 --- a/projects/fmcadc2/zc706/system_top.v +++ b/projects/fmcadc2/zc706/system_top.v @@ -84,6 +84,7 @@ module system_top ( sys_clk_p, sys_clk_n, + sys_rst, hdmi_out_clk, hdmi_vsync, @@ -159,6 +160,7 @@ module system_top ( input sys_clk_p; input sys_clk_n; + input sys_rst; output hdmi_out_clk; output hdmi_vsync; @@ -323,7 +325,8 @@ module system_top ( .spi_sdo_i (1'b0), .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p)); + .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst)); endmodule From d483801e2d4dbcd6a4b11eeca33fdb6eddb3350c Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:06:29 +0200 Subject: [PATCH 16/22] daq3_zc706: Delete trailing spaces from system_top --- projects/daq3/zc706/system_top.v | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 4d6983bf1..0465aaae7 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -90,7 +90,7 @@ module system_top ( hdmi_hsync, hdmi_data_e, hdmi_data, - + spdif, iic_scl, @@ -104,7 +104,7 @@ module system_top ( rx_sync_n, rx_data_p, rx_data_n, - + tx_ref_clk_p, tx_ref_clk_n, tx_sysref_p, @@ -113,7 +113,7 @@ module system_top ( tx_sync_n, tx_data_p, tx_data_n, - + trig_p, trig_n, @@ -121,12 +121,12 @@ module system_top ( adc_fda, dac_irq, clkd_status, - + adc_pd, dac_txen, sysref_p, sysref_n, - + spi_csn_clk, spi_csn_dac, spi_csn_adc, @@ -183,7 +183,7 @@ module system_top ( output hdmi_hsync; output hdmi_data_e; output [23:0] hdmi_data; - + output spdif; inout iic_scl; @@ -197,7 +197,7 @@ module system_top ( output rx_sync_n; input [ 3:0] rx_data_p; input [ 3:0] rx_data_n; - + input tx_ref_clk_p; input tx_ref_clk_n; input tx_sysref_p; @@ -206,7 +206,7 @@ module system_top ( input tx_sync_n; output [ 3:0] tx_data_p; output [ 3:0] tx_data_n; - + input trig_p; input trig_n; @@ -214,12 +214,12 @@ module system_top ( inout adc_fda; inout dac_irq; inout [ 1:0] clkd_status; - + inout adc_pd; inout dac_txen; output sysref_p; output sysref_n; - + output spi_csn_clk; output spi_csn_dac; output spi_csn_adc; @@ -235,7 +235,7 @@ module system_top ( reg adc_dsync = 'd0; reg adc_dwr = 'd0; reg [127:0] adc_ddata = 'd0; - + // internal signals wire sysref; From d77e28e372b7c059d77066a1a342f23218605855 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:07:52 +0200 Subject: [PATCH 17/22] daq3_zc706: Connect PLDDR rst to external push button --- projects/daq3/zc706/system_bd.tcl | 3 +++ projects/daq3/zc706/system_top.v | 3 +++ 2 files changed, 6 insertions(+) diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index 401e1e9d9..53e407d56 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -4,8 +4,11 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 +create_bd_port -dir I -type rst sys_rst +set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9680_fifo/sys_rst] connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk] create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] \ diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 0465aaae7..03262dac8 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -43,6 +43,7 @@ module system_top ( sys_clk_p, sys_clk_n, + sys_rst, DDR3_addr, DDR3_ba, @@ -136,6 +137,7 @@ module system_top ( input sys_clk_p; input sys_clk_n; + input sys_rst; output [13:0] DDR3_addr; output [ 2:0] DDR3_ba; @@ -539,6 +541,7 @@ module system_top ( .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), .tx_data_n (tx_data_n), .tx_data_p (tx_data_p), .tx_ref_clk (tx_ref_clk), From 362b0f53002dc24ee7156f41f5c392f219ef9f12 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:08:33 +0200 Subject: [PATCH 18/22] daq3_zc706: Add constraint file for PLDDR --- projects/daq3/zc706/system_project.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/daq3/zc706/system_project.tcl b/projects/daq3/zc706/system_project.tcl index 0f761db52..2f4859d1a 100644 --- a/projects/daq3/zc706/system_project.tcl +++ b/projects/daq3/zc706/system_project.tcl @@ -10,6 +10,7 @@ adi_project_files daq3_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] From a0b83bac7fe3dbc86b8b3f8ffbebb3d848c265f0 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:13:16 +0200 Subject: [PATCH 19/22] fmcomms7_zc706: Delete trailing spaces from system top --- projects/fmcomms7/zc706/system_top.v | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/projects/fmcomms7/zc706/system_top.v b/projects/fmcomms7/zc706/system_top.v index fbb17fd1d..65365dc27 100644 --- a/projects/fmcomms7/zc706/system_top.v +++ b/projects/fmcomms7/zc706/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -90,7 +90,7 @@ module system_top ( hdmi_hsync, hdmi_data_e, hdmi_data, - + spdif, iic_scl, @@ -104,7 +104,7 @@ module system_top ( rx_sync_n, rx_data_p, rx_data_n, - + tx_ref_clk_p, tx_ref_clk_n, tx_sysref_p, @@ -115,7 +115,7 @@ module system_top ( tx_sync1_n, tx_data_p, tx_data_n, - + trig_p, trig_n, @@ -283,7 +283,7 @@ module system_top ( reg adc_dsync = 'd0; reg adc_dwr = 'd0; reg [127:0] adc_ddata = 'd0; - + // internal signals wire trig; From 6e124c4c241ffd1b5fb6c0947fe76436989ed6e4 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:14:32 +0200 Subject: [PATCH 20/22] fmcomms7_zc706: Connect PLDDR rst to external push button --- projects/fmcomms7/zc706/system_bd.tcl | 3 +++ projects/fmcomms7/zc706/system_top.v | 3 +++ 2 files changed, 6 insertions(+) diff --git a/projects/fmcomms7/zc706/system_bd.tcl b/projects/fmcomms7/zc706/system_bd.tcl index a4bf1b618..00f86e2f3 100644 --- a/projects/fmcomms7/zc706/system_bd.tcl +++ b/projects/fmcomms7/zc706/system_bd.tcl @@ -4,8 +4,11 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128 +create_bd_port -dir I -type rst sys_rst +set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9680_fifo/sys_rst] connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk] create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] \ diff --git a/projects/fmcomms7/zc706/system_top.v b/projects/fmcomms7/zc706/system_top.v index 65365dc27..881b28c1b 100644 --- a/projects/fmcomms7/zc706/system_top.v +++ b/projects/fmcomms7/zc706/system_top.v @@ -43,6 +43,7 @@ module system_top ( sys_clk_p, sys_clk_n, + sys_rst, DDR3_addr, DDR3_ba, @@ -159,6 +160,7 @@ module system_top ( input sys_clk_p; input sys_clk_n; + input sys_rst; output [ 13:0] DDR3_addr; output [ 2:0] DDR3_ba; @@ -667,6 +669,7 @@ module system_top ( .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), + .sys_rst (sys_rst), .tx_data_n (tx_data_n), .tx_data_p (tx_data_p), .tx_ref_clk (tx_ref_clk), From 6230cb25b7116ff663ebad65ef9f66928537b98f Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 10:15:11 +0200 Subject: [PATCH 21/22] fmcomms7_zc706: Add constraint file for PLDDR --- projects/fmcomms7/zc706/system_project.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/fmcomms7/zc706/system_project.tcl b/projects/fmcomms7/zc706/system_project.tcl index 40ecbdb8a..1e661326e 100644 --- a/projects/fmcomms7/zc706/system_project.tcl +++ b/projects/fmcomms7/zc706/system_project.tcl @@ -10,6 +10,7 @@ adi_project_files fmcomms7_zc706 [list \ "system_top.v" \ "system_constr.xdc"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] From 4a9c4cdf195e5e91b64d005a656e6c374a092626 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 18 Dec 2014 16:57:19 +0200 Subject: [PATCH 22/22] fmcadc2_zc706: Fix PLDDR fifo name --- projects/fmcadc2/zc706/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl index a4b798126..4e818d8db 100644 --- a/projects/fmcadc2/zc706/system_bd.tcl +++ b/projects/fmcadc2/zc706/system_bd.tcl @@ -8,7 +8,7 @@ create_bd_port -dir I -type rst sys_rst set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk -connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9680_fifo/sys_rst] +connect_bd_net -net sys_rst [get_bd_ports sys_rst] [get_bd_pins axi_ad9625_fifo/sys_rst] connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9625_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9625_fifo/sys_clk] create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_fifo/axi_fifo2s/axi] \