uzed: zed-copy
Rejeesh Kutty
parent
02cc926275
commit
a610ebb413
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# create board design
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# interface ports
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
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create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_fmc
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir O spi1_csn_2_o
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create_bd_port -dir O spi1_csn_1_o
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create_bd_port -dir O spi1_csn_0_o
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create_bd_port -dir I spi1_csn_i
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create_bd_port -dir I spi1_clk_i
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create_bd_port -dir O spi1_clk_o
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create_bd_port -dir I spi1_sdo_i
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create_bd_port -dir O spi1_sdo_o
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create_bd_port -dir I spi1_sdi_i
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create_bd_port -dir I -from 63 -to 0 gpio_i
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create_bd_port -dir O -from 63 -to 0 gpio_o
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create_bd_port -dir O -from 63 -to 0 gpio_t
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# hdmi interface
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create_bd_port -dir O hdmi_out_clk
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create_bd_port -dir O hdmi_hsync
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create_bd_port -dir O hdmi_vsync
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create_bd_port -dir O hdmi_data_e
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create_bd_port -dir O -from 15 -to 0 hdmi_data
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# i2s
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create_bd_port -dir O -type clk i2s_mclk
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create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
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# iic mux
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create_bd_port -dir I -from 1 -to 0 iic_mux_scl_i
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create_bd_port -dir O -from 1 -to 0 iic_mux_scl_o
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create_bd_port -dir O iic_mux_scl_t
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create_bd_port -dir I -from 1 -to 0 iic_mux_sda_i
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create_bd_port -dir O -from 1 -to 0 iic_mux_sda_o
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create_bd_port -dir O iic_mux_sda_t
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create_bd_port -dir I otg_vbusoc
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# spdif audio
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create_bd_port -dir O spdif
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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# instance: sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
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set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true} ] $axi_iic_main
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set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
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set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
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set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
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set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
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set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.C_M_AXIS_MM2S_TDATA_WIDTH {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_USE_MM2S_FSYNC {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.C_INCLUDE_S2MM {0}] $axi_hdmi_dma
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# audio peripherals
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen
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set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen
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set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
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set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_spdif_tx_core
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set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
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set_property -dict [list CONFIG.DMA_TYPE {1}] $axi_i2s_adi
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set_property -dict [list CONFIG.S_AXI_ADDRESS_WIDTH {16}] $axi_i2s_adi
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# iic (fmc)
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set axi_iic_fmc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_fmc]
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
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ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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# interface connections
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ad_connect ddr sys_ps7/DDR
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ad_connect gpio_i sys_ps7/GPIO_I
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ad_connect gpio_o sys_ps7/GPIO_O
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ad_connect gpio_t sys_ps7/GPIO_T
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ad_connect fixed_io sys_ps7/FIXED_IO
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ad_connect iic_fmc axi_iic_fmc/iic
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ad_connect sys_200m_clk axi_hdmi_clkgen/clk
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ad_connect axi_iic_main/IIC sys_i2c_mixer/upstream
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ad_connect iic_mux_scl_i sys_i2c_mixer/downstream_scl_i
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ad_connect iic_mux_scl_o sys_i2c_mixer/downstream_scl_o
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ad_connect iic_mux_scl_t sys_i2c_mixer/downstream_scl_t
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ad_connect iic_mux_sda_i sys_i2c_mixer/downstream_sda_i
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ad_connect iic_mux_sda_o sys_i2c_mixer/downstream_sda_o
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ad_connect iic_mux_sda_t sys_i2c_mixer/downstream_sda_t
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ad_connect sys_logic_inv/Res sys_ps7/USB0_VBUS_PWRFAULT
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ad_connect otg_vbusoc sys_logic_inv/Op1
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# spi connections
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ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
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ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
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ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
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ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
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ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
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ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
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ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
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ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
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ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
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ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
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ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
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ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
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ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
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ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
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ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
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ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
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ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
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ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
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# hdmi
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ad_connect sys_cpu_clk axi_hdmi_core/vdma_clk
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ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
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ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
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ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
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ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
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ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync
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ad_connect axi_hdmi_core/hdmi_16_data_e hdmi_data_e
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ad_connect axi_hdmi_core/hdmi_16_data hdmi_data
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ad_connect axi_hdmi_core/vdma_valid axi_hdmi_dma/m_axis_mm2s_tvalid
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ad_connect axi_hdmi_core/vdma_data axi_hdmi_dma/m_axis_mm2s_tdata
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ad_connect axi_hdmi_core/vdma_ready axi_hdmi_dma/m_axis_mm2s_tready
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ad_connect axi_hdmi_core/vdma_fs axi_hdmi_dma/mm2s_fsync
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ad_connect axi_hdmi_core/vdma_fs axi_hdmi_core/vdma_fs_ret
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# spdif audio
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ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
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ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
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ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
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ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
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ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
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ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
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ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
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ad_connect spdif axi_spdif_tx_core/spdif_tx_o
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# i2s audio
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
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ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK
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ad_connect sys_cpu_clk sys_ps7/DMA2_ACLK
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ad_connect sys_audio_clkgen/clk_out1 i2s_mclk
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ad_connect sys_audio_clkgen/clk_out1 axi_i2s_adi/DATA_CLK_I
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ad_connect i2s axi_i2s_adi/I2S
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ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
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ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
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ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
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ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
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ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
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# interrupts
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ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
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ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
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ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In13 ps_intr_13
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ad_connect sys_concat_intc/In12 ps_intr_12
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ad_connect sys_concat_intc/In11 axi_iic_fmc/iic2intc_irpt
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ad_connect sys_concat_intc/In10 ps_intr_10
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ad_connect sys_concat_intc/In9 ps_intr_09
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ad_connect sys_concat_intc/In8 ps_intr_08
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ad_connect sys_concat_intc/In7 ps_intr_07
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ad_connect sys_concat_intc/In6 ps_intr_06
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ad_connect sys_concat_intc/In5 ps_intr_05
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ad_connect sys_concat_intc/In4 ps_intr_04
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ad_connect sys_concat_intc/In3 ps_intr_03
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ad_connect sys_concat_intc/In2 ps_intr_02
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ad_connect sys_concat_intc/In1 ps_intr_01
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ad_connect sys_concat_intc/In0 ps_intr_00
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# interconnects and address mapping
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ad_cpu_interconnect 0x41600000 axi_iic_main
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ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
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ad_cpu_interconnect 0x43000000 axi_hdmi_dma
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ad_cpu_interconnect 0x70e00000 axi_hdmi_core
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ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
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ad_cpu_interconnect 0x77600000 axi_i2s_adi
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ad_cpu_interconnect 0x41620000 axi_iic_fmc
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ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
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ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
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@ -0,0 +1,89 @@
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# constraints
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# hdmi
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set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS33} [get_ports hdmi_out_clk]
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set_property -dict {PACKAGE_PIN W17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_vsync]
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_hsync]
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set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data_e]
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set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[0]]
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set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[1]]
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set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[2]]
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set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[3]]
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set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[4]]
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set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[5]]
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set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[6]]
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set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[7]]
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set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[8]]
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set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[9]]
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set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[10]]
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set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[11]]
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set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[12]]
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set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[13]]
|
||||
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[14]]
|
||||
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports hdmi_data[15]]
|
||||
|
||||
# spdif
|
||||
|
||||
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spdif]
|
||||
|
||||
# i2s
|
||||
|
||||
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS33} [get_ports i2s_mclk]
|
||||
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVCMOS33} [get_ports i2s_bclk]
|
||||
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS33} [get_ports i2s_lrclk]
|
||||
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_out]
|
||||
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS33} [get_ports i2s_sdata_in]
|
||||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports iic_sda]
|
||||
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[1]]
|
||||
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[1]]
|
||||
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_scl[0]]
|
||||
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 PULLTYPE PULLUP} [get_ports iic_mux_sda[0]]
|
||||
|
||||
# otg
|
||||
|
||||
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS25} [get_ports otg_vbusoc]
|
||||
|
||||
# gpio (switches, leds and such)
|
||||
|
||||
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## BTNC
|
||||
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## BTND
|
||||
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## BTNL
|
||||
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## BTNR
|
||||
set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## BTNU
|
||||
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]] ; ## OLED-DC
|
||||
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS33} [get_ports gpio_bd[6]] ; ## OLED-RES
|
||||
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[7]] ; ## OLED-SCLK
|
||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[8]] ; ## OLED-SDIN
|
||||
set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]] ; ## OLED-VBAT
|
||||
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]] ; ## OLED-VDD
|
||||
|
||||
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[11]] ; ## SW0
|
||||
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[12]] ; ## SW1
|
||||
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS25} [get_ports gpio_bd[13]] ; ## SW2
|
||||
set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[14]] ; ## SW3
|
||||
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS25} [get_ports gpio_bd[15]] ; ## SW4
|
||||
set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports gpio_bd[16]] ; ## SW5
|
||||
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[17]] ; ## SW6
|
||||
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[18]] ; ## SW7
|
||||
|
||||
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[19]] ; ## LD0
|
||||
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[20]] ; ## LD1
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[21]] ; ## LD2
|
||||
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[22]] ; ## LD3
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[23]] ; ## LD4
|
||||
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports gpio_bd[24]] ; ## LD5
|
||||
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[25]] ; ## LD6
|
||||
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports gpio_bd[26]] ; ## LD7
|
||||
|
||||
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[27]] ; ## XADC-GIO0
|
||||
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[28]] ; ## XADC-GIO1
|
||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[29]] ; ## XADC-GIO2
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports gpio_bd[30]] ; ## XADC-GIO3
|
||||
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[31]] ; ## OTG-RESETN
|
||||
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
|
||||
set_property CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_RESET_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_ENET0_RESET_IO {MIO 47} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_USB0_RESET_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_USB0_RESET_IO {MIO 7} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_I2C0_I2C0_IO {MIO 50 .. 51} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_I2C0_RESET_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_I2C0_RESET_IO {MIO 46} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_SD0_GRP_CD_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_SD0_GRP_CD_IO {MIO 14} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_SD0_GRP_WP_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {50} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_QSPI_GRP_IO1_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_CL {7} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_CWL {5} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_T_RCD {7} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_T_RP {7} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_T_RC {49.5} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {36.0} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_T_FAW {45.0} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.078} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.074} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.059} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.055} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.482} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.484} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.417} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.416} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_16_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_17_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_18_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_19_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_20_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_21_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_22_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_23_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_24_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_25_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_26_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_27_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
|
||||
set_property CONFIG.PCW_MIO_28_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_29_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_30_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_31_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_32_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_33_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_34_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_35_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_36_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_37_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_38_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_39_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_40_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_41_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_42_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_43_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_44_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_45_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_48_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_49_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_52_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
set_property CONFIG.PCW_MIO_53_PULLUP {disabled} [get_bd_cells sys_ps7]
|
||||
|
||||
|
||||
Loading…
Reference in New Issue