From a5e3a073750affb1e6cdc79ec89928ea2c536dc7 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 11 Aug 2014 15:57:47 -0400 Subject: [PATCH] dma: altera fix id assignments --- library/axi_ad9652/axi_ad9652.v | 390 ++++++++++++++++++++++++ library/axi_ad9652/axi_ad9652_channel.v | 214 +++++++++++++ library/axi_ad9652/axi_ad9652_if.v | 288 +++++++++++++++++ library/axi_ad9652/axi_ad9652_ip.tcl | 31 ++ library/axi_ad9652/axi_ad9652_pnmon.v | 189 ++++++++++++ library/axi_dmac/axi_dmac_alt.v | 4 +- 6 files changed, 1114 insertions(+), 2 deletions(-) create mode 100755 library/axi_ad9652/axi_ad9652.v create mode 100755 library/axi_ad9652/axi_ad9652_channel.v create mode 100755 library/axi_ad9652/axi_ad9652_if.v create mode 100755 library/axi_ad9652/axi_ad9652_ip.tcl create mode 100755 library/axi_ad9652/axi_ad9652_pnmon.v diff --git a/library/axi_ad9652/axi_ad9652.v b/library/axi_ad9652/axi_ad9652.v new file mode 100755 index 000000000..8ace7f193 --- /dev/null +++ b/library/axi_ad9652/axi_ad9652.v @@ -0,0 +1,390 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9652 ( + + // adc interface (clk, data, over-range) + + adc_clk_in_p, + adc_clk_in_n, + adc_data_in_p, + adc_data_in_n, + adc_or_in_p, + adc_or_in_n, + + // delay interface + + delay_clk, + + // dma interface + + adc_clk, + adc_valid_0, + adc_enable_0, + adc_data_0, + adc_valid_1, + adc_enable_1, + adc_data_1, + adc_dovf, + adc_dunf, + up_adc_gpio_in, + up_adc_gpio_out, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + // parameters + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_ADC_DP_DISABLE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + parameter C_HIGHADDR = 32'hffffffff; + parameter C_BASEADDR = 32'h00000000; + + // adc interface (clk, data, over-range) + + input adc_clk_in_p; + input adc_clk_in_n; + input [15:0] adc_data_in_p; + input [15:0] adc_data_in_n; + input adc_or_in_p; + input adc_or_in_n; + + // delay interface + + input delay_clk; + + // dma interface + + output adc_clk; + output adc_valid_0; + output adc_enable_0; + output [15:0] adc_data_0; + output adc_valid_1; + output adc_enable_1; + output [15:0] adc_data_1; + input adc_dovf; + input adc_dunf; + input [31:0] up_adc_gpio_in; + output [31:0] up_adc_gpio_out; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_ack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + + // internal signals + + wire [15:0] adc_data_a_s; + wire [15:0] adc_data_b_s; + wire adc_or_a_s; + wire adc_or_b_s; + wire [15:0] adc_dcfilter_data_a_s; + wire [15:0] adc_dcfilter_data_b_s; + wire [15:0] adc_channel_data_a_s; + wire [15:0] adc_channel_data_b_s; + wire [ 1:0] up_status_pn_err_s; + wire [ 1:0] up_status_pn_oos_s; + wire [ 1:0] up_status_or_s; + wire adc_ddr_edgesel_s; + wire adc_status_s; + wire delay_rst_s; + wire delay_sel_s; + wire delay_rwn_s; + wire [ 7:0] delay_addr_s; + wire [ 4:0] delay_wdata_s; + wire [ 4:0] delay_rdata_s; + wire delay_ack_t_s; + wire delay_locked_s; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:2]; + wire up_ack_s[0:2]; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // dma interface + + assign adc_valid_0 = 1'b1; + assign adc_valid_1 = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1]; + up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1]; + up_status_or <= up_status_or_s[0] | up_status_or_s[1]; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2]; + end + end + + // channel + + axi_ad9652_channel #( + .IQSEL(0), + .CHID(0), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_a_s), + .adc_or (adc_or_a_s), + .adc_dcfilter_data_out (adc_dcfilter_data_a_s), + .adc_dcfilter_data_in (adc_dcfilter_data_b_s), + .adc_iqcor_data (adc_data_0), + .adc_enable (adc_enable_0), + .up_adc_pn_err (up_status_pn_err_s[0]), + .up_adc_pn_oos (up_status_pn_oos_s[0]), + .up_adc_or (up_status_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[0]), + .up_ack (up_ack_s[0])); + + // channel + + axi_ad9652_channel #( + .IQSEL(1), + .CHID(1), + .DP_DISABLE (PCORE_ADC_DP_DISABLE)) + i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_b_s), + .adc_or (adc_or_b_s), + .adc_dcfilter_data_out (adc_dcfilter_data_b_s), + .adc_dcfilter_data_in (adc_dcfilter_data_a_s), + .adc_iqcor_data (adc_data_1), + .adc_enable (adc_enable_1), + .up_adc_pn_err (up_status_pn_err_s[1]), + .up_adc_pn_oos (up_status_pn_oos_s[1]), + .up_adc_or (up_status_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[1]), + .up_ack (up_ack_s[1])); + + // main (device interface) + + axi_ad9652_if #( + .PCORE_BUFTYPE (PCORE_DEVICE_TYPE), + .PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP)) + i_if ( + .adc_clk_in_p (adc_clk_in_p), + .adc_clk_in_n (adc_clk_in_n), + .adc_data_in_p (adc_data_in_p), + .adc_data_in_n (adc_data_in_n), + .adc_or_in_p (adc_or_in_p), + .adc_or_in_n (adc_or_in_n), + .adc_clk (adc_clk), + .adc_data_a (adc_data_a_s), + .adc_data_b (adc_data_b_s), + .adc_or_a (adc_or_a_s), + .adc_or_b (adc_or_b_s), + .adc_status (adc_status_s), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst_s), + .delay_sel (delay_sel_s), + .delay_rwn (delay_rwn_s), + .delay_addr (delay_addr_s), + .delay_wdata (delay_wdata_s), + .delay_rdata (delay_rdata_s), + .delay_ack_t (delay_ack_t_s), + .delay_locked (delay_locked_s)); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd1), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .delay_clk (delay_clk), + .delay_rst (delay_rst_s), + .delay_sel (delay_sel_s), + .delay_rwn (delay_rwn_s), + .delay_addr (delay_addr_s), + .delay_wdata (delay_wdata_s), + .delay_rdata (delay_rdata_s), + .delay_ack_t (delay_ack_t_s), + .delay_locked (delay_locked_s), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd0), + .up_adc_gpio_in (up_adc_gpio_in), + .up_adc_gpio_out (up_adc_gpio_out), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[2]), + .up_ack (up_ack_s[2])); + + // up bus interface + + up_axi #( + .PCORE_BASEADDR (C_BASEADDR), + .PCORE_HIGHADDR (C_HIGHADDR)) + i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9652/axi_ad9652_channel.v b/library/axi_ad9652/axi_ad9652_channel.v new file mode 100755 index 000000000..fe7d1ba07 --- /dev/null +++ b/library/axi_ad9652/axi_ad9652_channel.v @@ -0,0 +1,214 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9652_channel ( + + // adc interface + + adc_clk, + adc_rst, + adc_data, + adc_or, + + // channel interface + + adc_dcfilter_data_out, + adc_dcfilter_data_in, + adc_iqcor_data, + adc_enable, + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter IQSEL = 0; + parameter CHID = 0; + parameter DP_DISABLE = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [15:0] adc_data; + input adc_or; + + // channel interface + + output [15:0] adc_dcfilter_data_out; + input [15:0] adc_dcfilter_data_in; + output [15:0] adc_iqcor_data; + output adc_enable; + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + // processor interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal signals + + wire [15:0] adc_dcfilter_data_i_s; + wire [15:0] adc_dcfilter_data_q_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + // iq correction inputs + + assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in : adc_dcfilter_data_out; + assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in; + + axi_ad9652_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + generate + if (DP_DISABLE == 1) begin + assign adc_dcfilter_data_out = adc_data; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data), + .valid_out (), + .data_out (adc_dcfilter_data_out), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + endgenerate + + generate + if (DP_DISABLE == 1) begin + assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s; + end else begin + ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor ( + .clk (adc_clk), + .valid (1'b1), + .data_i (adc_dcfilter_data_i_s), + .data_q (adc_dcfilter_data_q_s), + .valid_out (), + .data_out (adc_iqcor_data), + .iqcor_enable (adc_iqcor_enb_s), + .iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (), + .adc_dfmt_type (), + .adc_dfmt_enable (), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9652/axi_ad9652_if.v b/library/axi_ad9652/axi_ad9652_if.v new file mode 100755 index 000000000..0ff3b69c9 --- /dev/null +++ b/library/axi_ad9652/axi_ad9652_if.v @@ -0,0 +1,288 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface, note that overrange is independent of data path, +// software will not be able to relate overrange to a specific sample! +// Alternative is to concatenate sample value and or status for data. + +`timescale 1ns/100ps + +module axi_ad9652_if ( + + // adc interface (clk, data, over-range) + + adc_clk_in_p, + adc_clk_in_n, + adc_data_in_p, + adc_data_in_n, + adc_or_in_p, + adc_or_in_n, + + // interface outputs + + adc_clk, + adc_data_a, + adc_data_b, + adc_or_a, + adc_or_b, + adc_status, + + // processor control signals + + adc_ddr_edgesel, + + // delay control signals + + delay_clk, + delay_rst, + delay_sel, + delay_rwn, + delay_addr, + delay_wdata, + delay_rdata, + delay_ack_t, + delay_locked); + + // This parameter controls the buffer type based on the target device. + + parameter PCORE_BUFTYPE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + + // adc interface (clk, data, over-range) + + input adc_clk_in_p; + input adc_clk_in_n; + input [15:0] adc_data_in_p; + input [15:0] adc_data_in_n; + input adc_or_in_p; + input adc_or_in_n; + + // interface outputs + + output adc_clk; + output [15:0] adc_data_a; + output [15:0] adc_data_b; + output adc_or_a; + output adc_or_b; + output adc_status; + + // processor control signals + + input adc_ddr_edgesel; + + // delay control signals + + input delay_clk; + input delay_rst; + input delay_sel; + input delay_rwn; + input [ 7:0] delay_addr; + input [ 4:0] delay_wdata; + output [ 4:0] delay_rdata; + output delay_ack_t; + output delay_locked; + + // internal registers + + reg adc_status = 'd0; + reg [15:0] adc_data_p = 'd0; + reg [15:0] adc_data_n = 'd0; + reg [15:0] adc_data_p_d = 'd0; + reg adc_or_p = 'd0; + reg adc_or_n = 'd0; + reg adc_or_p_d = 'd0; + reg [15:0] adc_data_a = 'd0; + reg [15:0] adc_data_b = 'd0; + reg adc_or_a = 'd0; + reg adc_or_b = 'd0; + reg [16:0] delay_ld = 'd0; + reg delay_ack_t = 'd0; + reg [ 4:0] delay_rdata = 'd0; + + // internal signals + + wire [ 4:0] delay_rdata_s[16:0]; + wire [15:0] adc_data_p_s; + wire [15:0] adc_data_n_s; + wire adc_or_p_s; + wire adc_or_n_s; + + genvar l_inst; + + // two data pin modes are supported- + // mux - across clock edges (rising or falling edges), + // mux - within clock edges (lower 7 bits and upper 7 bits) + + always @(posedge adc_clk) begin + adc_status <= 1'b1; + adc_data_p <= adc_data_p_s; + adc_data_n <= adc_data_n_s; + adc_data_p_d <= adc_data_p; + adc_or_p <= adc_or_p_s; + adc_or_n <= adc_or_n_s; + adc_or_p_d <= adc_or_p; + end + + always @(posedge adc_clk) begin + if (adc_ddr_edgesel == 1'b1) begin + adc_data_a <= adc_data_p_d; + adc_data_b <= adc_data_n; + adc_or_a <= adc_or_p_d; + adc_or_b <= adc_or_n; + end else begin + adc_data_a <= adc_data_n; + adc_data_b <= adc_data_p; + adc_or_a <= adc_or_n; + adc_or_b <= adc_or_p; + end + end + + // delay write interface, each delay element can be individually + // addressed, and a delay value can be directly loaded (no inc/dec stuff) + + always @(posedge delay_clk) begin + if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin + case (delay_addr) + 8'h10: delay_ld <= 17'h10000; + 8'h0f: delay_ld <= 17'h08000; + 8'h0e: delay_ld <= 17'h04000; + 8'h0d: delay_ld <= 17'h02000; + 8'h0c: delay_ld <= 17'h01000; + 8'h0b: delay_ld <= 17'h00800; + 8'h0a: delay_ld <= 17'h00400; + 8'h09: delay_ld <= 17'h00200; + 8'h08: delay_ld <= 17'h00100; + 8'h07: delay_ld <= 17'h00080; + 8'h06: delay_ld <= 17'h00040; + 8'h05: delay_ld <= 17'h00020; + 8'h04: delay_ld <= 17'h00010; + 8'h03: delay_ld <= 17'h00008; + 8'h02: delay_ld <= 17'h00004; + 8'h01: delay_ld <= 17'h00002; + 8'h00: delay_ld <= 17'h00001; + default: delay_ld <= 17'h00000; + endcase + end else begin + delay_ld <= 15'h0000; + end + end + + // delay read interface, a delay ack toggle is used to transfer data to the + // processor side- delay locked is independently transferred + + always @(posedge delay_clk) begin + case (delay_addr) + 8'h10: delay_rdata <= delay_rdata_s[16]; + 8'h0f: delay_rdata <= delay_rdata_s[15]; + 8'h0e: delay_rdata <= delay_rdata_s[14]; + 8'h0d: delay_rdata <= delay_rdata_s[13]; + 8'h0c: delay_rdata <= delay_rdata_s[12]; + 8'h0b: delay_rdata <= delay_rdata_s[11]; + 8'h0a: delay_rdata <= delay_rdata_s[10]; + 8'h09: delay_rdata <= delay_rdata_s[ 9]; + 8'h08: delay_rdata <= delay_rdata_s[ 8]; + 8'h07: delay_rdata <= delay_rdata_s[ 7]; + 8'h06: delay_rdata <= delay_rdata_s[ 6]; + 8'h05: delay_rdata <= delay_rdata_s[ 5]; + 8'h04: delay_rdata <= delay_rdata_s[ 4]; + 8'h03: delay_rdata <= delay_rdata_s[ 3]; + 8'h02: delay_rdata <= delay_rdata_s[ 2]; + 8'h01: delay_rdata <= delay_rdata_s[ 1]; + 8'h00: delay_rdata <= delay_rdata_s[ 0]; + default: delay_rdata <= 5'd0; + endcase + if (delay_sel == 1'b1) begin + delay_ack_t <= ~delay_ack_t; + end + end + + // data interface + + generate + for (l_inst = 0; l_inst <= 15; l_inst = l_inst + 1) begin : g_adc_if + ad_lvds_in #( + .BUFTYPE (PCORE_BUFTYPE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + i_adc_data ( + .rx_clk (adc_clk), + .rx_data_in_p (adc_data_in_p[l_inst]), + .rx_data_in_n (adc_data_in_n[l_inst]), + .rx_data_p (adc_data_p_s[l_inst]), + .rx_data_n (adc_data_n_s[l_inst]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_ld (delay_ld[l_inst]), + .delay_wdata (delay_wdata), + .delay_rdata (delay_rdata_s[l_inst]), + .delay_locked ()); + end + endgenerate + + // over-range interface + + ad_lvds_in #( + .BUFTYPE (PCORE_BUFTYPE), + .IODELAY_CTRL (1), + .IODELAY_GROUP (PCORE_IODELAY_GROUP)) + i_adc_or ( + .rx_clk (adc_clk), + .rx_data_in_p (adc_or_in_p), + .rx_data_in_n (adc_or_in_n), + .rx_data_p (adc_or_p_s), + .rx_data_n (adc_or_n_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_ld (delay_ld[16]), + .delay_wdata (delay_wdata), + .delay_rdata (delay_rdata_s[16]), + .delay_locked (delay_locked)); + + // clock + + ad_lvds_clk #( + .BUFTYPE (PCORE_BUFTYPE)) + i_adc_clk ( + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9652/axi_ad9652_ip.tcl b/library/axi_ad9652/axi_ad9652_ip.tcl new file mode 100755 index 000000000..d25b31604 --- /dev/null +++ b/library/axi_ad9652/axi_ad9652_ip.tcl @@ -0,0 +1,31 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9652 +adi_ip_files axi_ad9652 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ + "$ad_hdl_dir/library/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "axi_ad9652_pnmon.v" \ + "axi_ad9652_channel.v" \ + "axi_ad9652_if.v" \ + "axi_ad9652.v" ] + +adi_ip_properties axi_ad9652 + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9652/axi_ad9652_pnmon.v b/library/axi_ad9652/axi_ad9652_pnmon.v new file mode 100755 index 000000000..4c62389a8 --- /dev/null +++ b/library/axi_ad9652/axi_ad9652_pnmon.v @@ -0,0 +1,189 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9652_pnmon ( + + // adc interface + + adc_clk, + adc_data, + + // pn out of sync and error + + adc_pn_oos, + adc_pn_err, + adc_pnseq_sel); + + // adc interface + + input adc_clk; + input [15:0] adc_data; + + // pn out of sync and error + + output adc_pn_oos; + output adc_pn_err; + input [ 3:0] adc_pnseq_sel; + + // internal registers + + reg adc_valid_in = 'd0; + reg [31:0] adc_pn_data_in = 'd0; + reg [31:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [31:0] adc_pn_data_pn_s; + + // PN23 function + + function [31:0] pn23; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[22] ^ din[17]; + dout[30] = din[21] ^ din[16]; + dout[29] = din[20] ^ din[15]; + dout[28] = din[19] ^ din[14]; + dout[27] = din[18] ^ din[13]; + dout[26] = din[17] ^ din[12]; + dout[25] = din[16] ^ din[11]; + dout[24] = din[15] ^ din[10]; + dout[23] = din[14] ^ din[ 9]; + dout[22] = din[13] ^ din[ 8]; + dout[21] = din[12] ^ din[ 7]; + dout[20] = din[11] ^ din[ 6]; + dout[19] = din[10] ^ din[ 5]; + dout[18] = din[ 9] ^ din[ 4]; + dout[17] = din[ 8] ^ din[ 3]; + dout[16] = din[ 7] ^ din[ 2]; + dout[15] = din[ 6] ^ din[ 1]; + dout[14] = din[ 5] ^ din[ 0]; + dout[13] = din[ 4] ^ din[22] ^ din[17]; + dout[12] = din[ 3] ^ din[21] ^ din[16]; + dout[11] = din[ 2] ^ din[20] ^ din[15]; + dout[10] = din[ 1] ^ din[19] ^ din[14]; + dout[ 9] = din[ 0] ^ din[18] ^ din[13]; + dout[ 8] = din[22] ^ din[12]; + dout[ 7] = din[21] ^ din[11]; + dout[ 6] = din[20] ^ din[10]; + dout[ 5] = din[19] ^ din[ 9]; + dout[ 4] = din[18] ^ din[ 8]; + dout[ 3] = din[17] ^ din[ 7]; + dout[ 2] = din[16] ^ din[ 6]; + dout[ 1] = din[15] ^ din[ 5]; + dout[ 0] = din[14] ^ din[ 4]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [31:0] pn9; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + adc_valid_in <= ~adc_valid_in; + adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]}; + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(32)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_valid_in), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_dmac/axi_dmac_alt.v b/library/axi_dmac/axi_dmac_alt.v index 9fb9e9627..1d9cefbf3 100755 --- a/library/axi_dmac/axi_dmac_alt.v +++ b/library/axi_dmac/axi_dmac_alt.v @@ -353,8 +353,8 @@ module axi_dmac_alt ( // defaults - assign s_axi_bid = 'd0; - assign s_axi_rid = 'd0; + assign s_axi_bid = s_axi_awid; + assign s_axi_rid = s_axi_arid; assign s_axi_rlast = 1'd0; // instantiation