Add axi_generic_adc core
The axi_generic_adc core is a simple core that doesn't do much more then implementing the AXI ADC register map and routing the enable and overflow signals to the farbic. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
033713ccb5
commit
a5b452cc27
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@ -30,6 +30,7 @@ clean:
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make -C axi_adcfifo clean
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make -C axi_clkgen clean
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make -C axi_dmac clean
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make -C axi_generic_adc clean
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make -C axi_hdmi_rx clean
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make -C axi_hdmi_tx clean
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make -C axi_i2s_adi clean
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@ -82,6 +83,7 @@ lib:
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-make -C axi_adcfifo
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-make -C axi_clkgen
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-make -C axi_dmac
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-make -C axi_generic_adc
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-make -C axi_hdmi_rx
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-make -C axi_hdmi_tx
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-make -C axi_i2s_adi
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@ -0,0 +1,51 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS := axi_generic_adc_ip.tcl
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M_DEPS += ../scripts/adi_env.tcl
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M_DEPS += ../scripts/adi_ip.tcl
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M_DEPS += ../common/ad_rst.v
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M_DEPS += ../common/up_axi.v
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M_DEPS += ../common/up_delay_cntrl.v
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M_DEPS += ../common/up_drp_cntrl.v
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M_DEPS += ../common/up_xfer_cntrl.v
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M_DEPS += ../common/up_xfer_status.v
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M_DEPS += ../common/up_clock_mon.v
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M_DEPS += ../common/up_adc_channel.v
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M_DEPS += ../common/up_adc_common.v
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M_DEPS += axi_generic_adc.v
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += component.xml
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += .Xil
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.PHONY: all clean clean-all
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all: axi_generic_adc.xpr
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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axi_generic_adc.xpr: $(M_DEPS)
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rm -rf $(M_FLIST)
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$(M_VIVADO) axi_generic_adc_ip.tcl >> axi_generic_adc_ip.log 2>&1
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####################################################################################
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####################################################################################
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@ -0,0 +1,205 @@
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module axi_generic_adc (
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input adc_clk,
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output [NUM_CHANNELS-1:0] adc_enable,
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input adc_dovf,
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready
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);
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parameter NUM_CHANNELS = 2;
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parameter PCORE_ID = 0;
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reg [31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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// internal signals
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_s[0:NUM_CHANNELS];
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wire up_rack_s[0:NUM_CHANNELS];
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wire up_wack_s[0:NUM_CHANNELS];
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reg [31:0] up_rdata_r;
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reg up_rack_r;
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reg up_wack_r;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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integer j;
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always @(*)
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begin
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up_rdata_r = 'h00;
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up_rack_r = 'h00;
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up_wack_r = 'h00;
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for (j = 0; j <= NUM_CHANNELS; j=j+1) begin
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up_rack_r = up_rack_r | up_rack_s[j];
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up_wack_r = up_wack_r | up_wack_s[j];
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up_rdata_r = up_rdata_r | up_rdata_s[j];
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_rdata <= up_rdata_r;
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up_rack <= up_rack_r;
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up_wack <= up_wack_r;
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end
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end
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up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status ('h00),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (1'b0),
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.adc_clk_ratio (32'd1),
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.up_status_pn_err (1'b0),
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.up_status_pn_oos (1'b0),
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.up_status_or (1'b0),
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.drp_clk (1'd0),
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.drp_rst (),
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.drp_sel (),
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.drp_wr (),
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.drp_addr (),
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.drp_wdata (),
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.drp_rdata (16'd0),
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.drp_ready (1'd0),
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.drp_locked (1'd1),
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.up_usr_chanmax (),
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.adc_usr_chanmax (8'd0),
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.up_adc_gpio_in (),
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[NUM_CHANNELS]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[NUM_CHANNELS]),
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.up_rack (up_rack_s[NUM_CHANNELS]));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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generate
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genvar i;
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for (i = 0; i < NUM_CHANNELS; i=i+1) begin
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up_adc_channel #(.PCORE_ADC_CHID(i)) i_up_adc_channel (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_enable (adc_enable[i]),
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.adc_iqcor_enb (),
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.adc_dcfilt_enb (),
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.adc_dfmt_se (),
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.adc_dfmt_type (),
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.adc_dfmt_enable (),
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.adc_dcfilt_offset (),
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.adc_dcfilt_coeff (),
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.adc_iqcor_coeff_1 (),
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.adc_iqcor_coeff_2 (),
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.adc_pnseq_sel (),
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.adc_data_sel (),
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.adc_pn_err (),
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.adc_pn_oos (),
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.adc_or (),
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.up_adc_pn_err (),
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.up_adc_pn_oos (),
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.up_adc_or (),
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.up_usr_datatype_be (),
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.up_usr_datatype_signed (),
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.up_usr_datatype_shift (),
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.up_usr_datatype_total_bits (),
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.up_usr_datatype_bits (),
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.up_usr_decimation_m (),
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.up_usr_decimation_n (),
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.adc_usr_datatype_be (1'b0),
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.adc_usr_datatype_signed (1'b1),
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.adc_usr_datatype_shift (8'd0),
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.adc_usr_datatype_total_bits (8'd32),
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.adc_usr_datatype_bits (8'd32),
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.adc_usr_decimation_m (16'd1),
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.adc_usr_decimation_n (16'd1),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[i]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[i]),
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.up_rack (up_rack_s[i]));
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end
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endgenerate
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endmodule
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@ -0,0 +1,24 @@
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_generic_adc
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adi_ip_files axi_generic_adc [list \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
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"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"axi_generic_adc.v" \
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]
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adi_ip_properties axi_generic_adc
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ipx::save_core [ipx::current_core]
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