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axi_dmac: early abort 2d support

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Laszlo Nagy 2018-08-30 14:29:24 +01:00 committed by Laszlo Nagy
parent a1cc20e3b9
commit a4c4e384bb
4 changed files with 14 additions and 0 deletions
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4
library/axi_dmac/2d_transfer.v
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@ -62,6 +62,8 @@ module dmac_2d_transfer #(
output reg req_response_valid, output reg req_response_valid,
input req_response_ready, input req_response_ready,
input out_abort_req,
output reg out_req_valid, output reg out_req_valid,
input out_req_ready, input out_req_ready,
output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address, output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
@ -158,6 +160,8 @@ always @(posedge req_aclk) begin
src_stride <= req_src_stride; src_stride <= req_src_stride;
out_req_sync_transfer_start <= req_sync_transfer_start; out_req_sync_transfer_start <= req_sync_transfer_start;
gen_last <= req_last; gen_last <= req_last;
end else if (out_abort_req == 1'b1) begin
y_length <= 0;
end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];

4
library/axi_dmac/axi_dmac_transfer.v
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@ -205,6 +205,7 @@ wire src_enabled;
wire req_valid_gated; wire req_valid_gated;
wire req_ready_gated; wire req_ready_gated;
wire abort_req;
axi_dmac_reset_manager #( axi_dmac_reset_manager #(
.ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC), .ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC),
@ -274,6 +275,7 @@ dmac_2d_transfer #(
.req_sync_transfer_start (req_sync_transfer_start), .req_sync_transfer_start (req_sync_transfer_start),
.req_last (req_last), .req_last (req_last),
.out_abort_req (abort_req),
.out_req_valid (dma_req_valid), .out_req_valid (dma_req_valid),
.out_req_ready (dma_req_ready), .out_req_ready (dma_req_ready),
.out_req_dest_address (dma_req_dest_address), .out_req_dest_address (dma_req_dest_address),
@ -348,6 +350,8 @@ dmac_request_arb #(
.response_valid (dma_response_valid), .response_valid (dma_response_valid),
.response_ready (dma_response_ready), .response_ready (dma_response_ready),
.abort_req (abort_req),
.req_enable (req_enable), .req_enable (req_enable),
.dest_clk (dest_clk), .dest_clk (dest_clk),

4
library/axi_dmac/request_arb.v
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@ -72,6 +72,8 @@ module dmac_request_arb #(
output response_valid, output response_valid,
input response_ready, input response_ready,
output abort_req,
// Master AXI interface // Master AXI interface
input m_dest_axi_aclk, input m_dest_axi_aclk,
input m_dest_axi_aresetn, input m_dest_axi_aresetn,
@ -1116,6 +1118,8 @@ dmac_request_generator #(
.rewind_req_data(req_rewind_req_data), .rewind_req_data(req_rewind_req_data),
.rewind_state(rewind_state), .rewind_state(rewind_state),
.abort_req(abort_req),
.completion_req_valid(completion_req_valid), .completion_req_valid(completion_req_valid),
.completion_req_last(completion_req_last), .completion_req_last(completion_req_last),
.completion_transfer_id(completion_transfer_id), .completion_transfer_id(completion_transfer_id),

2
library/axi_dmac/request_generator.v
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@ -248,4 +248,6 @@ assign completion_transfer_id = rew_transfer_id;
assign rewind_state = (state == STATE_REWIND_ID); assign rewind_state = (state == STATE_REWIND_ID);
assign abort_req = (state == STATE_REWIND_ID) && !rew_req_xlast && !cur_req_xlast;
endmodule endmodule