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ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems 

For ZC706 Fixed one constraint which was not correct
main
Adrian Costina 2014-08-26 16:28:41 +03:00
parent 58fa0776c9
commit a49eb5853b
4 changed files with 14 additions and 4 deletions
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6
projects/common/zc702/zc702_system_constr.xdc
View File

@ -60,8 +60,12 @@ create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0] create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1] create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
create_clock -name ps7_clk_0 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]]
create_clock -name ps7_clk_1 -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]]
set_clock_groups -asynchronous -group {cpu_clk} set_clock_groups -asynchronous -group {cpu_clk}
set_clock_groups -asynchronous -group {m200_clk} set_clock_groups -asynchronous -group {m200_clk}
set_clock_groups -asynchronous -group {hdmi_clk} set_clock_groups -asynchronous -group {hdmi_clk}
set_clock_groups -asynchronous -group {spdif_clk} set_clock_groups -asynchronous -group {spdif_clk}
set_clock_groups -asynchronous -group {ps7_clk_0}
set_clock_groups -asynchronous -group {ps7_clk_1}

4
projects/common/zc706/zc706_system_constr.xdc
View File

@ -67,8 +67,8 @@ create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0] create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1] create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
create_clock -name ps7_clk_0 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]] create_clock -name ps7_clk_0 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]]
create_clock -name ps7_clk_1 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]] create_clock -name ps7_clk_1 -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]]
set_clock_groups -asynchronous -group {cpu_clk} set_clock_groups -asynchronous -group {cpu_clk}
set_clock_groups -asynchronous -group {m200_clk} set_clock_groups -asynchronous -group {m200_clk}

6
projects/common/zed/zed_system_constr.xdc
View File

@ -94,8 +94,12 @@ create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0] create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1] create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
create_clock -name ps7_clk_0 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]]
create_clock -name ps7_clk_1 -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]]
set_clock_groups -asynchronous -group {cpu_clk} set_clock_groups -asynchronous -group {cpu_clk}
set_clock_groups -asynchronous -group {m200_clk} set_clock_groups -asynchronous -group {m200_clk}
set_clock_groups -asynchronous -group {hdmi_clk} set_clock_groups -asynchronous -group {hdmi_clk}
set_clock_groups -asynchronous -group {spdif_clk} set_clock_groups -asynchronous -group {spdif_clk}
set_clock_groups -asynchronous -group {ps7_clk_0}
set_clock_groups -asynchronous -group {ps7_clk_1}

2
projects/fmcomms5/zc702/system_constr.xdc Normal file → Executable file
View File

@ -134,7 +134,9 @@ create_clock -name rx_0_clk -period 5.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 5.00 [get_ports rx_clk_in_1_p] create_clock -name rx_1_clk -period 5.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk] create_clock -name ad9361_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name ps7_clk_2 -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]]
set_clock_groups -asynchronous -group {ad9361_clk} set_clock_groups -asynchronous -group {ad9361_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk} set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {ps7_clk_2}