diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v
index 71a041163..acb5fb093 100644
--- a/library/axi_ad9361/axi_ad9361.v
+++ b/library/axi_ad9361/axi_ad9361.v
@@ -108,6 +108,8 @@ module axi_ad9361 (
   dac_dunf,
   dac_r1_mode,
 
+  tdd_enable,
+
   enable,
   txnrx,
 
@@ -222,6 +224,8 @@ module axi_ad9361 (
   input           dac_dunf;
   output          dac_r1_mode;
 
+  output          tdd_enable;
+
   output          enable;
   output          txnrx;
 
@@ -397,6 +401,7 @@ module axi_ad9361 (
     .tdd_tx_vco_en(tdd_tx_vco_en_s),
     .tdd_rx_rf_en(tdd_rx_rf_en_s),
     .tdd_tx_rf_en(tdd_tx_rf_en_s),
+    .tdd_enable (tdd_enable),
     .tdd_status(tdd_status_s),
     .tx_valid_i0(dac_valid_i0_s),
     .tx_valid_q0(dac_valid_q0_s),
diff --git a/library/axi_ad9361/axi_ad9361_tdd.v b/library/axi_ad9361/axi_ad9361_tdd.v
index 24b814ad6..40c2e325e 100644
--- a/library/axi_ad9361/axi_ad9361_tdd.v
+++ b/library/axi_ad9361/axi_ad9361_tdd.v
@@ -55,6 +55,7 @@ module axi_ad9361_tdd (
 
   // status signal
 
+  tdd_enable,
   tdd_status,
 
   // tx data flow control
@@ -95,6 +96,7 @@ module axi_ad9361_tdd (
   output            tdd_rx_rf_en;
   output            tdd_tx_rf_en;
 
+  output            tdd_enable;
   input   [ 7:0]    tdd_status;
 
   // tx data flow control
@@ -169,6 +171,8 @@ module axi_ad9361_tdd (
   assign  tdd_tx_valid_i1 = (tdd_enable_s == 1'b1) ? (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1;
   assign  tdd_tx_valid_q1 = (tdd_enable_s == 1'b1) ? (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1;
 
+  assign  tdd_enable = tdd_enable_s;
+
   // instantiations
 
   up_tdd_cntrl i_up_tdd_cntrl(