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projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2 

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
main
Michael Hennerich 2014-09-16 14:58:09 +02:00
parent c927e90ee1
commit a3dbd5ac00
2 changed files with 16 additions and 14 deletions
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6
projects/ad9625_fmc/common/ad9625_fmc_bd.tcl
View File

@ -35,7 +35,7 @@ if {$sys_zynq == 0} {
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9625_jesd]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9625_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
@ -81,7 +81,7 @@ if {$sys_zynq == 0} {
set_property -dict [list CONFIG.C_GPIO_WIDTH {2}] $axi_ad9625_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad9625_gpio
set axi_ad9625_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_ad9625_spi]
set axi_ad9625_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad9625_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
@ -277,7 +277,7 @@ if {$sys_zynq == 1} {
# ila
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon

24
projects/common/vc707/vc707_system_bd.tcl
View File

@ -41,7 +41,7 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
# instance: microblaze - processor
set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 sys_mb]
set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.3 sys_mb]
set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $sys_mb
set_property -dict [list CONFIG.C_D_AXI {1}] $sys_mb
set_property -dict [list CONFIG.C_D_LMB {1}] $sys_mb
@ -52,7 +52,7 @@ set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb
set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb
set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb
set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb
set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {4}] $sys_mb
set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb
set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
@ -73,23 +73,23 @@ set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 sys_lmb_bram]
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.2 sys_lmb_bram]
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
# instance: microblaze- mdm
set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 sys_mb_debug]
set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.1 sys_mb_debug]
set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
# instance: system reset/clocks
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 sys_const_vcc]
# instance: ddr (mig)
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl]
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.1 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/vc707/vc707_system_mig.prj "$axi_ddr_cntrl_dir/"
set_property -dict [list CONFIG.XML_INPUT_FILE {vc707_system_mig.prj}] $axi_ddr_cntrl
@ -113,8 +113,10 @@ set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect
# instance: default peripherals
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.0 axi_ethernet]
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.1 axi_ethernet]
set_property -dict [list CONFIG.PHY_TYPE {SGMII}] $axi_ethernet
set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
@ -146,11 +148,11 @@ set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_sw_led
set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_aux_intc]
set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_aux_intc]
set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_aux_intc
set_property -dict [list CONFIG.IN9_WIDTH {5}] $sys_concat_aux_intc
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
# hdmi peripherals
@ -158,7 +160,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
@ -354,7 +356,7 @@ connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get
# defaults (external interface)
connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/const] [get_bd_ports fan_pwm] [get_bd_pins axi_ethernet/signal_detect]
connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/dout] [get_bd_ports fan_pwm] [get_bd_pins axi_ethernet/signal_detect]
connect_bd_net -net sys_rst_s [get_bd_ports sys_rst]
connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in]
connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst]