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ad_ip_jesd204_tpl_dac: Add 8 bit resolution support

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Istvan Csomortani 2019-03-12 13:44:06 +00:00 committed by István Csomortáni
parent e3e96177c4
commit a337774dfa
5 changed files with 13 additions and 9 deletions
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4
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
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@ -83,7 +83,7 @@ module ad_ip_jesd204_tpl_dac #(
localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE;
localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8;
localparam DMA_DATA_WIDTH = 16 * DATA_PATH_WIDTH * NUM_CHANNELS;
localparam DMA_DATA_WIDTH = BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS;
localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES);
@ -165,6 +165,8 @@ module ad_ip_jesd204_tpl_dac #(
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),

5
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
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@ -27,6 +27,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
parameter DATAPATH_DISABLE = 0,
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16,
parameter BITS_PER_SAMPLE = 16,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16
@ -35,7 +36,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
input clk,
input [DATA_PATH_WIDTH*16-1:0] dma_data,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dma_data,
output reg [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] dac_data = 'h00,
// PN data
@ -93,7 +94,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
genvar i;
/* Data is expected to be LSB aligned, drop unused MSBs */
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_dac_dma_data
assign dac_dma_data_s[CR*i+:CR] = dma_data[16*i+:CR];
assign dac_dma_data_s[CR*i+:CR] = dma_data[BITS_PER_SAMPLE*i+:CR];
end
endgenerate

5
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
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@ -33,7 +33,7 @@ module ad_ip_jesd204_tpl_dac_core #(
parameter OCTETS_PER_BEAT = 4,
parameter DATA_PATH_WIDTH = 4,
parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * 16 * NUM_CHANNELS,
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * BITS_PER_SAMPLE * NUM_CHANNELS,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16
@ -71,7 +71,7 @@ module ad_ip_jesd204_tpl_dac_core #(
localparam DAC_CDW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
localparam DAC_DATA_WIDTH = DAC_CDW * NUM_CHANNELS;
localparam DMA_CDW = DATA_PATH_WIDTH * 16;
localparam DMA_CDW = DATA_PATH_WIDTH * BITS_PER_SAMPLE;
assign link_valid = 1'b1;
@ -120,6 +120,7 @@ module ad_ip_jesd204_tpl_dac_core #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW)

4
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
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@ -104,14 +104,14 @@ ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 false [list \
DISPLAY_NAME "Bits per Sample (N')" \
ALLOWED_RANGES {12 16} \
ALLOWED_RANGES {8 12 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \
DISPLAY_NAME "Converter Resolution (N)" \
ALLOWED_RANGES {11 12 16} \
ALLOWED_RANGES {8 11 12 16} \
UNITS bits \
GROUP $group \
]

4
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
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@ -88,8 +88,8 @@ foreach p {DDS_CORDIC_DW DDS_CORDIC_PHASE_DW} {
foreach {p v} {
"NUM_LANES" "1 2 3 4 8" \
"NUM_CHANNELS" "1 2 4 6 8" \
"BITS_PER_SAMPLE" "12 16" \
"CONVERTER_RESOLUTION" "11 12 16" \
"BITS_PER_SAMPLE" "8 12 16" \
"CONVERTER_RESOLUTION" "8 11 12 16" \
"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
"OCTETS_PER_BEAT" "4 8" \
} { \