zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_dacfifo: Delete unused registers/nets

main
Istvan Csomortani 2018-06-12 16:31:10 +01:00
parent dd912e1fb8
commit a2fc1f25ca
3 changed files with 0 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
library/xilinx/axi_dacfifo/axi_dacfifo.v
View File

@ -117,13 +117,9 @@ module axi_dacfifo #(
reg dac_xfer_out_m1 = 1'b0;
reg dac_xfer_out_bypass = 1'b0;
wire [(AXI_DATA_WIDTH-1):0] axi_rd_data_s;
wire axi_rd_ready_s;
wire axi_rd_valid_s;
wire axi_xfer_req_s;
(* dont_touch = "true" *) wire [31:0] axi_last_addr_s;
(* dont_touch = "true" *) wire [ 7:0] axi_last_beats_s;
wire axi_dlast_s;
wire [ 3:0] dma_last_beats_s;
wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s;
wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s;

8
library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
View File

@ -105,13 +105,7 @@ module axi_dacfifo_rd #(
// internal registers
reg axi_ractive = 1'b0;
reg [ 1:0] axi_xfer_req_m = 2'b0;
reg [ 7:0] axi_last_beats_cntr = 8'b0;
reg axi_data_req = 1'b0;
reg [(AXI_DATA_WIDTH-1):0] axi_ddata = 'b0;
reg axi_dlast = 1'b0;
reg axi_dvalid = 1'b0;
reg [ 4:0] axi_read_state = 5'b0;
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;
reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0;
@ -147,12 +141,10 @@ module axi_dacfifo_rd #(
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_b2g_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_b2g_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2_g2b_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_m2_g2b_s;
wire [ DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;
wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_s;

1
library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
View File

@ -171,7 +171,6 @@ module axi_dacfifo_wr #(
wire axi_waddr_ready_s;
wire axi_wready_s;
wire axi_partial_burst_s;
wire axi_last_burst_s;
wire axi_xlast_s;
wire axi_reset_s;