diff --git a/projects/daq2/a10gx/system_bd.qsys b/projects/daq2/a10gx/system_bd.qsys
index eb6934cc4..84e091117 100755
--- a/projects/daq2/a10gx/system_bd.qsys
+++ b/projects/daq2/a10gx/system_bd.qsys
@@ -115,6 +115,14 @@
          type = "String";
       }
    }
+   element signaltap_ii_logic_analyzer_0
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+   }
    element sys_clk
    {
       datum _sortIndex
@@ -573,6 +581,30 @@
          type = "String";
       }
    }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element system_bd
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
    element util_cpack_0
    {
       datum _sortIndex
@@ -650,21 +682,7 @@
    internal="axi_jesd_xcvr.if_rx_ext_sysref"
    type="conduit"
    dir="end" />
- <interface
-   name="stp_clk"
-   internal="axi_jesd_xcvr.if_stp_clk"
-   type="clock"
-   dir="start" />
- <interface
-   name="stp_data"
-   internal="axi_jesd_xcvr.if_stp_data"
-   type="conduit"
-   dir="end" />
- <interface
-   name="stp_trigger"
-   internal="axi_jesd_xcvr.if_stp_trigger"
-   type="conduit"
-   dir="end" />
+ <interface name="stp_trigger" internal="axi_jesd_xcvr.if_stp_trigger" />
  <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
  <interface
    name="sys_ddr3_cntrl_mem"
@@ -800,8 +818,30 @@
   <parameter name="PCORE_ID" value="0" />
   <parameter name="PCORE_NUM_OF_RX_LANES" value="4" />
   <parameter name="PCORE_NUM_OF_TX_LANES" value="4" />
-  <parameter name="PCORE_ST_DATA_WIDTH" value="32" />
-  <parameter name="PCORE_ST_TRIGGER_WIDTH" value="32" />
+  <parameter name="PCORE_ST_DATA_WIDTH" value="182" />
+  <parameter name="PCORE_ST_TRIGGER_WIDTH" value="2" />
+ </module>
+ <module
+   name="signaltap_ii_logic_analyzer_0"
+   kind="altera_signaltap_ii_logic_analyzer"
+   version="15.0"
+   enabled="1">
+  <parameter name="device_family" value="Arria 10" />
+  <parameter name="gui_num_segments" value="2" />
+  <parameter name="gui_ram_type" value="AUTO" />
+  <parameter name="gui_sq" value="Continuous" />
+  <parameter name="gui_trigger_out_enabled" value="false" />
+  <parameter name="gui_use_segmented" value="false" />
+  <parameter name="sld_data_bits" value="182" />
+  <parameter name="sld_enable_advanced_trigger" value="0" />
+  <parameter name="sld_node_crc_bits" value="32" />
+  <parameter name="sld_node_info" value="806383104" />
+  <parameter name="sld_sample_depth" value="1024" />
+  <parameter name="sld_storage_qualifier_gap_record" value="0" />
+  <parameter name="sld_trigger_bits" value="2" />
+  <parameter name="sld_trigger_in_enabled" value="0" />
+  <parameter name="sld_trigger_level" value="1" />
+  <parameter name="sld_trigger_level_pipeline" value="1" />
  </module>
  <module name="sys_clk" kind="clock_source" version="15.0" enabled="1">
   <parameter name="clockFrequency" value="100000000" />
@@ -810,8 +850,8 @@
   <parameter name="resetSynchronousEdges" value="NONE" />
  </module>
  <module name="sys_cpu" kind="altera_nios2_gen2" version="15.0" enabled="1">
-  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="3" />
-  <parameter name="AUTO_CLK_RESET_DOMAIN" value="3" />
+  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="2" />
+  <parameter name="AUTO_CLK_RESET_DOMAIN" value="2" />
   <parameter name="AUTO_DEVICE" value="10AX115S3F45I2SGE2" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
   <parameter name="bht_ramBlockType" value="Automatic" />
@@ -2320,6 +2360,11 @@
    version="15.0"
    start="axi_jesd_xcvr.if_rx_clk"
    end="axi_ad9680_core.if_rx_clk" />
+ <connection
+   kind="clock"
+   version="15.0"
+   start="axi_jesd_xcvr.if_stp_clk"
+   end="signaltap_ii_logic_analyzer_0.acq_clk" />
  <connection
    kind="clock"
    version="15.0"
@@ -2555,6 +2600,17 @@
   <parameter name="startPortLSB" value="0" />
   <parameter name="width" value="0" />
  </connection>
+ <connection
+   kind="conduit"
+   version="15.0"
+   start="axi_jesd_xcvr.if_stp"
+   end="signaltap_ii_logic_analyzer_0.tap">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="conduit"
    version="15.0"
diff --git a/projects/daq2/a10gx/system_constr.sdc b/projects/daq2/a10gx/system_constr.sdc
index 5828874c9..048bb06f5 100644
--- a/projects/daq2/a10gx/system_constr.sdc
+++ b/projects/daq2/a10gx/system_constr.sdc
@@ -6,7 +6,14 @@ create_clock -period "2.000 ns"   -name rx_ref_clk_500mhz   [get_ports {rx_ref_c
 create_clock -period "2.000 ns"   -name tx_ref_clk_500mhz   [get_ports {tx_ref_clk}]
 
 derive_pll_clocks
+
+create_generated_clock -source {i_system_bd|axi_jesd_xcvr|i_sys_xcvr|i_rx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|refclk[0]} \
+  -divide_by 8 -multiply_by 4 -duty_cycle 50.00 -name {i_system_bd|axi_jesd_xcvr|rx_clk} \
+  {i_system_bd|axi_jesd_xcvr|i_sys_xcvr|i_rx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|outclk[0]}
+
+create_generated_clock -source {i_system_bd|axi_jesd_xcvr|i_sys_xcvr|i_tx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|refclk[0]} \
+  -divide_by 8 -multiply_by 4 -duty_cycle 50.00 -name {i_system_bd|axi_jesd_xcvr|tx_clk} \
+  {i_system_bd|axi_jesd_xcvr|i_sys_xcvr|i_tx_pll|iopll_0|altera_pll_i|general[0].gpll~IOPLL|outclk[0]}
+
 derive_clock_uncertainty
 
-
-
diff --git a/projects/daq2/a10gx/system_project.tcl b/projects/daq2/a10gx/system_project.tcl
index 367f44b8c..7c011e267 100755
--- a/projects/daq2/a10gx/system_project.tcl
+++ b/projects/daq2/a10gx/system_project.tcl
@@ -9,13 +9,13 @@ source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
 set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
 set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
 set_global_assignment -name VERILOG_FILE ../common/sys_xcvr.v
-set_global_assignment -name QSYS_FILE ../common/sys_xcvr_tx_lane_pll.qsys
-set_global_assignment -name QSYS_FILE ../common/sys_xcvr_core.qsys
-set_global_assignment -name QSYS_FILE ../common/sys_xcvr_rstcntrl.qsys
-set_global_assignment -name QSYS_FILE ../common/sys_xcvr_rx_pll.qsys
-set_global_assignment -name QSYS_FILE ../common/sys_xcvr_tx_pll.qsys
-set_global_assignment -name QSYS_FILE ../common/sys_xcvr_rx_ip.qsys
-set_global_assignment -name QSYS_FILE ../common/sys_xcvr_tx_ip.qsys
+set_global_assignment -name QSYS_FILE sys_xcvr_tx_lane_pll.qsys
+set_global_assignment -name QSYS_FILE sys_xcvr_core.qsys
+set_global_assignment -name QSYS_FILE sys_xcvr_rstcntrl.qsys
+set_global_assignment -name QSYS_FILE sys_xcvr_rx_pll.qsys
+set_global_assignment -name QSYS_FILE sys_xcvr_tx_pll.qsys
+set_global_assignment -name QSYS_FILE sys_xcvr_rx_ip.qsys
+set_global_assignment -name QSYS_FILE sys_xcvr_tx_ip.qsys
 
 # lane interface
 
diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v
index 428d5f6a7..8aeaf0c6a 100644
--- a/projects/daq2/a10gx/system_top.v
+++ b/projects/daq2/a10gx/system_top.v
@@ -243,9 +243,6 @@ module system_top (
     .rx_ref_clk_clk (rx_ref_clk),
     .rx_sync_rx_sync (rx_sync),
     .rx_sysref_rx_ext_sysref (rx_sysref),
-    .stp_clk_clk (),
-    .stp_data_stp_data (),
-    .stp_trigger_stp_trigger (),
     .sys_clk_clk (sys_clk),
     .sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
     .sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
diff --git a/projects/daq2/common/sys_xcvr.v b/projects/daq2/common/sys_xcvr.v
index 656c7c015..01b9539d4 100644
--- a/projects/daq2/common/sys_xcvr.v
+++ b/projects/daq2/common/sys_xcvr.v
@@ -112,8 +112,8 @@ module sys_xcvr (
   output            tx_int;
 
   output            stp_clk;
-  output  [ 31:0]   stp_data;
-  output  [  3:0]   stp_trigger;
+  output  [181:0]   stp_data;
+  output  [  1:0]   stp_trigger;
                                                              
   // internal signals
 
@@ -151,6 +151,21 @@ module sys_xcvr (
   wire    [ 15:0]   tx_pcs_kchar;
   wire    [127:0]   tx_pcs_data;
 
+  // signal tap
+
+  assign stp_clk = rx_clk;
+
+  assign stp_data[181:181] = rx_sysref;
+  assign stp_data[180:180] = rx_ip_sync;
+  assign stp_data[179:176] = rx_pcs_valid;
+  assign stp_data[175:160] = rx_pcs_disperr;
+  assign stp_data[159:144] = rx_pcs_errdetect;
+  assign stp_data[143:128] = rx_pcs_kchar;
+  assign stp_data[127:  0] = rx_pcs_data;
+
+  assign stp_trigger[1] = rx_sysref;
+  assign stp_trigger[0] = rx_ip_sync;
+
   // instantiations
 
   sys_xcvr_rx_pll i_rx_pll (