diff --git a/library/axi_adrv9009/axi_adrv9009.v b/library/axi_adrv9009/axi_adrv9009.v index 0b95ae1d7..86a172061 100644 --- a/library/axi_adrv9009/axi_adrv9009.v +++ b/library/axi_adrv9009/axi_adrv9009.v @@ -48,7 +48,11 @@ module axi_adrv9009 #( parameter ADC_OS_IQCORRECTION_DISABLE = 0, parameter DAC_DATAPATH_DISABLE = 0, parameter DAC_DDS_DISABLE = 0, - parameter DAC_IQCORRECTION_DISABLE = 0) ( + parameter DAC_IQCORRECTION_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 20, + parameter DAC_DDS_CORDIC_PHASE_DW = 18) ( + // receive @@ -299,7 +303,10 @@ module axi_adrv9009 #( axi_adrv9009_tx #( .ID (ID), .DDS_DISABLE (DAC_DDS_DISABLE_INT), - .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT)) + .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)) i_tx ( .dac_rst (dac_rst), .dac_clk (dac_clk), diff --git a/library/axi_adrv9009/axi_adrv9009_hw.tcl b/library/axi_adrv9009/axi_adrv9009_hw.tcl index f4b88fabd..7b4c7a715 100644 --- a/library/axi_adrv9009/axi_adrv9009_hw.tcl +++ b/library/axi_adrv9009/axi_adrv9009_hw.tcl @@ -19,6 +19,7 @@ add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/alt add_fileset_file ad_dds_cordic_pipe.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v add_fileset_file ad_dds_sine_cordic.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine_cordic.v add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v +add_fileset_file ad_dds_2.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_2.v add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v diff --git a/library/axi_adrv9009/axi_adrv9009_ip.tcl b/library/axi_adrv9009/axi_adrv9009_ip.tcl index 47a665622..93559fe95 100644 --- a/library/axi_adrv9009/axi_adrv9009_ip.tcl +++ b/library/axi_adrv9009/axi_adrv9009_ip.tcl @@ -16,6 +16,7 @@ adi_ip_files axi_adrv9009 [list \ "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ "$ad_hdl_dir/library/common/ad_dds.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ "$ad_hdl_dir/library/common/ad_iqcor.v" \ diff --git a/library/axi_adrv9009/axi_adrv9009_tx.v b/library/axi_adrv9009/axi_adrv9009_tx.v index 394bd1e55..1e0180525 100644 --- a/library/axi_adrv9009/axi_adrv9009_tx.v +++ b/library/axi_adrv9009/axi_adrv9009_tx.v @@ -41,8 +41,9 @@ module axi_adrv9009_tx #( parameter DISABLE = 0, parameter DDS_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0, - parameter DDS_TYPE = 1, - parameter DDS_CORDIC_DW = 16) ( + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 20, + parameter DAC_DDS_CORDIC_PHASE_DW = 18) ( // dac interface @@ -138,8 +139,9 @@ module axi_adrv9009_tx #( .DISABLE (DISABLE), .DDS_DISABLE (DDS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), - .DDS_TYPE (DDS_TYPE), - .DDS_CORDIC_DW (DDS_CORDIC_DW)) + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)) i_tx_channel_0 ( .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -171,8 +173,9 @@ module axi_adrv9009_tx #( .DISABLE (DISABLE), .DDS_DISABLE (DDS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), - .DDS_TYPE (DDS_TYPE), - .DDS_CORDIC_DW (DDS_CORDIC_DW)) + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)) i_tx_channel_1 ( .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -204,8 +207,9 @@ module axi_adrv9009_tx #( .DISABLE (DISABLE), .DDS_DISABLE (DDS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), - .DDS_TYPE (DDS_TYPE), - .DDS_CORDIC_DW (DDS_CORDIC_DW)) + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)) i_tx_channel_2 ( .dac_clk (dac_clk), .dac_rst (dac_rst), @@ -237,8 +241,9 @@ module axi_adrv9009_tx #( .DISABLE (DISABLE), .DDS_DISABLE (DDS_DISABLE), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), - .DDS_TYPE (DDS_TYPE), - .DDS_CORDIC_DW (DDS_CORDIC_DW)) + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW)) i_tx_channel_3 ( .dac_clk (dac_clk), .dac_rst (dac_rst), diff --git a/library/axi_adrv9009/axi_adrv9009_tx_channel.v b/library/axi_adrv9009/axi_adrv9009_tx_channel.v index 594521a5f..cf8f2727b 100644 --- a/library/axi_adrv9009/axi_adrv9009_tx_channel.v +++ b/library/axi_adrv9009/axi_adrv9009_tx_channel.v @@ -42,8 +42,9 @@ module axi_adrv9009_tx_channel #( parameter DISABLE = 0, parameter DDS_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0, - parameter DDS_TYPE = 1, - parameter DDS_CORDIC_DW = 16) ( + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 20, + parameter DAC_DDS_CORDIC_PHASE_DW = 18) ( // dac interface @@ -77,18 +78,10 @@ module axi_adrv9009_tx_channel #( // internal registers reg [31:0] dac_pat_data = 'd0; - reg [15:0] dac_dds_phase_0_0 = 'd0; - reg [15:0] dac_dds_phase_0_1 = 'd0; - reg [15:0] dac_dds_phase_1_0 = 'd0; - reg [15:0] dac_dds_phase_1_1 = 'd0; - reg [15:0] dac_dds_incr_0 = 'd0; - reg [15:0] dac_dds_incr_1 = 'd0; - reg [31:0] dac_dds_data = 'd0; // internal signals - wire [15:0] dac_dds_data_0_s; - wire [15:0] dac_dds_data_1_s; + wire [31:0] dac_dds_data_s; wire [15:0] dac_dds_scale_1_s; wire [15:0] dac_dds_init_1_s; wire [15:0] dac_dds_incr_1_s; @@ -143,7 +136,7 @@ module axi_adrv9009_tx_channel #( 4'h3: dac_data_iq_out <= 32'd0; 4'h2: dac_data_iq_out <= dac_data_in; 4'h1: dac_data_iq_out <= dac_pat_data; - default: dac_data_iq_out <= dac_dds_data; + default: dac_data_iq_out <= dac_dds_data_s; endcase end @@ -155,64 +148,26 @@ module axi_adrv9009_tx_channel #( // dds - always @(posedge dac_clk) begin - if (dac_data_sync == 1'b1) begin - dac_dds_phase_0_0 <= dac_dds_init_1_s; - dac_dds_phase_0_1 <= dac_dds_init_2_s; - dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s; - dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s; - dac_dds_incr_0 <= {dac_dds_incr_1_s[14:0], 1'd0}; - dac_dds_incr_1 <= {dac_dds_incr_2_s[14:0], 1'd0}; - dac_dds_data <= 32'd0; - end else begin - dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0; - dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1; - dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0; - dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1; - dac_dds_incr_0 <= dac_dds_incr_0; - dac_dds_incr_1 <= dac_dds_incr_1; - dac_dds_data <= {dac_dds_data_1_s, dac_dds_data_0_s}; - end - end - - // dds - - generate - if (DISABLE == 1 || DDS_DISABLE == 1) begin - - assign dac_dds_data_0_s = 16'd0; - assign dac_dds_data_1_s = 16'd0; - - end else begin - ad_dds #( - .DISABLE (0), - .DDS_TYPE (DDS_TYPE), - .CORDIC_DW (DDS_CORDIC_DW)) - i_dds_0 ( + .DISABLE (DDS_DISABLE), + .DDS_DW (16), + .PHASE_DW (16), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (2)) + i_dds ( .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_phase_0 (dac_dds_phase_0_0), - .dds_scale_0 (dac_dds_scale_1_s), - .dds_phase_1 (dac_dds_phase_0_1), - .dds_scale_1 (dac_dds_scale_2_s), - .dds_data (dac_dds_data_0_s)); - - ad_dds #( - .DISABLE (0), - .DDS_TYPE (DDS_TYPE), - .CORDIC_DW (DDS_CORDIC_DW)) - i_dds_1 ( - .clk (dac_clk), - .dds_format (dac_dds_format), - .dds_phase_0 (dac_dds_phase_1_0), - .dds_scale_0 (dac_dds_scale_1_s), - .dds_phase_1 (dac_dds_phase_1_1), - .dds_scale_1 (dac_dds_scale_2_s), - .dds_data (dac_dds_data_1_s)); - - end - endgenerate + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (1'b1), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); // single channel processor