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ad_serdes- altera/xilinx sync

main
Rejeesh Kutty 2016-09-15 13:33:55 -04:00
parent 67d4e71ff0
commit a2d15acb89
4 changed files with 322 additions and 456 deletions
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8
library/altera/common/ad_serdes_in.v
View File

@ -69,10 +69,10 @@ module ad_serdes_in #(
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
input up_clk;
input [(DATA_WIDTH-1):0] up_dld;
input [((DATA_WIDTH*5)-1):0] up_dwdata;
output [((DATA_WIDTH*5)-1):0] up_drdata;
// delay-control interface

76
library/xilinx/common/ad_serdes_clk.v
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@ -34,54 +34,35 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_clk (
// clock and divided clock
mmcm_rst,
clk_in_p,
clk_in_n,
clk,
div_clk,
out_clk,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
module ad_serdes_clk #(
// parameters
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFR_N = 1;
parameter MMCM_DEVICE_TYPE = 0;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter MMCM_OR_BUFR_N = 1,
parameter MMCM_DEVICE_TYPE = 0,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK1_DIV = 6) (
// clock and divided clock
input mmcm_rst;
input rst;
input clk_in_p;
input clk_in_n;
output clk;
output div_clk;
output out_clk;
output loaden;
output [ 7:0] phase,
// drp interface
@ -90,8 +71,8 @@ module ad_serdes_clk (
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
input [31:0] up_drp_wdata;
output [31:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
@ -99,6 +80,12 @@ module ad_serdes_clk (
wire clk_in_s;
// defaults
assign loaden = 'd0;
assign phase = 'd0;
assign up_drp_rdata[31:16] = 'd0;
// instantiations
IBUFGDS i_clk_in_ibuf (
@ -124,7 +111,7 @@ module ad_serdes_clk (
.clk (clk_in_s),
.clk2 (1'b0),
.clk_sel (1'b1),
.mmcm_rst (mmcm_rst),
.mmcm_rst (rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.mmcm_clk_2 (out_clk),
@ -133,24 +120,13 @@ module ad_serdes_clk (
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_wdata (up_drp_wdata[15:0]),
.up_drp_rdata (up_drp_rdata[15:0]),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
end
if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 0)) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (clk));
assign div_clk = clk;
assign out_clk = clk;
end
if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 1)) begin
if (MMCM_OR_BUFR_N == 0) begin
BUFIO i_clk_buf (
.I (clk_in_s),
.O (clk));

342
library/xilinx/common/ad_serdes_in.v
View File

@ -35,96 +35,67 @@
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_serdes_in (
// reset and clocks
rst,
clk,
div_clk,
// data interface
data_s0,
data_s1,
data_s2,
data_s3,
data_s4,
data_s5,
data_s6,
data_s7,
data_in_p,
data_in_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-control interface
delay_clk,
delay_rst,
delay_locked);
module ad_serdes_in #(
// parameters
parameter DEVICE_TYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
// SDR = 0 / DDR = 1
parameter DDR_OR_SDR_N = 0;
// serialization factor
parameter DATA_WIDTH = 8;
localparam DEVICE_6SERIES = 1;
localparam DEVICE_7SERIES = 0;
localparam SDR = 0;
localparam DDR = 1;
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 0,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// reset and clocks
input rst;
input clk;
input div_clk;
input loaden,
input [ 7:0] phase,
input locked,
// data interface
output data_s0;
output data_s1;
output data_s2;
output data_s3;
output data_s4;
output data_s5;
output data_s6;
output data_s7;
input data_in_p;
input data_in_n;
output [(DATA_WIDTH-1):0] data_s0;
output [(DATA_WIDTH-1):0] data_s1;
output [(DATA_WIDTH-1):0] data_s2;
output [(DATA_WIDTH-1):0] data_s3;
output [(DATA_WIDTH-1):0] data_s4;
output [(DATA_WIDTH-1):0] data_s5;
output [(DATA_WIDTH-1):0] data_s6;
output [(DATA_WIDTH-1):0] data_s7;
input [(DATA_WIDTH-1):0] data_in_p;
input [(DATA_WIDTH-1):0] data_in_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
input [(DATA_WIDTH-1):0] up_dld;
input [((DATA_WIDTH*5)-1):0] up_dwdata;
output [((DATA_WIDTH*5)-1):0] up_drdata;
// delay-control interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal signals
wire data_in_ibuf_s;
wire data_in_idelay_s;
wire data_shift1_s;
wire data_shift2_s;
wire [(DATA_WIDTH-1):0] data_in_ibuf_s;
wire [(DATA_WIDTH-1):0] data_in_idelay_s;
wire [(DATA_WIDTH-1):0] data_shift1_s;
wire [(DATA_WIDTH-1):0] data_shift2_s;
// parameters
localparam DEVICE_6SERIES = 1;
localparam DEVICE_7SERIES = 0;
localparam DATA_RATE = (DDR_OR_SDR_N == 1) ? "DDR" : "SDR";
// delay controller
@ -142,15 +113,17 @@ module ad_serdes_in (
// received data interface: ibuf -> idelay -> iserdes
genvar l_inst;
generate
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
IBUFDS i_ibuf (
.O(data_in_ibuf_s),
.I(data_in_p),
.IB(data_in_n)
);
.I (data_in_p[l_inst]),
.IB (data_in_n[l_inst]),
.O (data_in_ibuf_s[l_inst]));
if (DEVICE_TYPE == DEVICE_7SERIES) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
@ -160,7 +133,7 @@ module ad_serdes_in (
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
i_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
@ -168,115 +141,12 @@ module ad_serdes_in (
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.IDATAIN (data_in_ibuf_s),
.DATAOUT (data_in_idelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
// Note: The first sample in time will be data_s7, the last data_s0!
if(DDR_OR_SDR_N == SDR) begin
ISERDESE2 #(
.DATA_RATE("SDR"),
.DATA_WIDTH(DATA_WIDTH),
.DYN_CLKDIV_INV_EN("FALSE"),
.DYN_CLK_INV_EN("FALSE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(2),
.OFB_USED("FALSE"),
.SERDES_MODE("MASTER"),
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0))
ISERDESE2_inst (
.O(),
.Q1(data_s0),
.Q2(data_s1),
.Q3(data_s2),
.Q4(data_s3),
.Q5(data_s4),
.Q6(data_s5),
.Q7(data_s6),
.Q8(data_s7),
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0),
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0),
.CLK(clk),
.CLKB(~clk),
.CLKDIV(div_clk),
.OCLK(1'b0),
.DYNCLKDIVSEL(1'b0),
.DYNCLKSEL(1'b0),
.D(1'b0),
.DDLY(data_in_idelay_s),
.OFB(1'b0),
.OCLKB(1'b0),
.RST(rst),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
end else begin
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(DATA_WIDTH),
.DYN_CLKDIV_INV_EN("FALSE"),
.DYN_CLK_INV_EN("FALSE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(2),
.OFB_USED("FALSE"),
.SERDES_MODE("MASTER"),
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0))
ISERDESE2_inst (
.O(),
.Q1(data_s0),
.Q2(data_s1),
.Q3(data_s2),
.Q4(data_s3),
.Q5(data_s4),
.Q6(data_s5),
.Q7(data_s6),
.Q8(data_s7),
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0),
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0),
.CLK(clk),
.CLKB(~clk),
.CLKDIV(div_clk),
.OCLK(1'b0),
.DYNCLKDIVSEL(1'b0),
.DYNCLKSEL(1'b0),
.D(1'b0),
.DDLY(data_in_idelay_s),
.OFB(1'b0),
.OCLKB(1'b0),
.RST(rst),
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
.IDATAIN (data_in_ibuf_s[l_inst]),
.DATAOUT (data_in_idelay_s[l_inst]),
.LD (up_dld[l_inst]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)),
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)));
end
end
if(DEVICE_TYPE == DEVICE_6SERIES) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IODELAYE1 #(
@ -289,7 +159,7 @@ module ad_serdes_in (
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
i_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
@ -298,15 +168,66 @@ module ad_serdes_in (
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (up_clk),
.IDATAIN (data_in_ibuf_s),
.DATAOUT (data_in_idelay_s),
.RST (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
.IDATAIN (data_in_ibuf_s[l_inst]),
.DATAOUT (data_in_idelay_s[l_inst]),
.RST (up_dld[l_inst]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
end
if (DEVICE_TYPE == DEVICE_7SERIES) begin
ISERDESE2 #(
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (8),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.INIT_Q3 (1'b0),
.INIT_Q4 (1'b0),
.INTERFACE_TYPE ("NETWORKING"),
.IOBDELAY ("IFD"),
.NUM_CE (2),
.OFB_USED ("FALSE"),
.SERDES_MODE ("MASTER"),
.SRVAL_Q1 (1'b0),
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0))
i_iserdes (
.O (),
.Q1 (data_s0[l_inst]),
.Q2 (data_s1[l_inst]),
.Q3 (data_s2[l_inst]),
.Q4 (data_s3[l_inst]),
.Q5 (data_s4[l_inst]),
.Q6 (data_s5[l_inst]),
.Q7 (data_s6[l_inst]),
.Q8 (data_s7[l_inst]),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLKDIVP (1'b0),
.CLK (clk),
.CLKB (~clk),
.CLKDIV (div_clk),
.OCLK (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.D (1'b0),
.DDLY (data_in_idelay_s[l_inst]),
.OFB (1'b0),
.OCLKB (1'b0),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0));
end
if (DEVICE_TYPE == DEVICE_6SERIES) begin
ISERDESE1 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(DATA_WIDTH),
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (8),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
@ -322,36 +243,35 @@ module ad_serdes_in (
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0))
i_serdes_m (
i_iserdes_m (
.O (),
.Q1(data_s0),
.Q2(data_s1),
.Q3(data_s2),
.Q4(data_s3),
.Q5(data_s4),
.Q6(data_s5),
.SHIFTOUT1(data_shift1_s),
.SHIFTOUT2(data_shift2_s),
.Q1 (data_s0[l_inst]),
.Q2 (data_s1[l_inst]),
.Q3 (data_s2[l_inst]),
.Q4 (data_s3[l_inst]),
.Q5 (data_s4[l_inst]),
.Q6 (data_s5[l_inst]),
.SHIFTOUT1 (data_shift1_s[l_inst]),
.SHIFTOUT2 (data_shift2_s[l_inst]),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (clk),
.CLKB(1'b0),
.CLKB (~clk),
.CLKDIV (div_clk),
.OCLK (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.D(data_in_idelay_s),
.DDLY(1'b0),
.D (1'b0),
.DDLY (data_in_idelay_s[l_inst]),
.OFB (1'b0),
.RST (rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2(1'b0)
);
.SHIFTIN2 (1'b0));
ISERDESE1 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(DATA_WIDTH),
.DATA_RATE (DATA_RATE),
.DATA_WIDTH (8),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.INIT_Q1 (1'b0),
@ -367,12 +287,12 @@ module ad_serdes_in (
.SRVAL_Q2 (1'b0),
.SRVAL_Q3 (1'b0),
.SRVAL_Q4 (1'b0))
i_serdes_s (
i_iserdes_s (
.O (),
.Q1 (),
.Q2 (),
.Q3(data_s6),
.Q4(data_s7),
.Q3 (data_s6[l_inst]),
.Q4 (data_s7[l_inst]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
@ -381,18 +301,22 @@ module ad_serdes_in (
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (clk),
.CLKB(1'b0),
.CLKB (~clk),
.CLKDIV (div_clk),
.OCLK (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.D (1'b0),
.DDLY(1'b0),
.DDLY (data_in_idelay_s[l_inst]),
.OFB (1'b0),
.RST (rst),
.SHIFTIN1(data_shift1_s),
.SHIFTIN2(data_shift2_s));
.SHIFTIN1 (data_shift1_s[l_inst]),
.SHIFTIN2 (data_shift2_s[l_inst]));
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

90
library/xilinx/common/ad_serdes_out.v
View File

@ -34,91 +34,57 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_out (
// reset and clocks
rst,
clk,
div_clk,
// data interface
data_s0,
data_s1,
data_s2,
data_s3,
data_s4,
data_s5,
data_s6,
data_s7,
data_out_p,
data_out_n);
module ad_serdes_out #(
// parameters
parameter DEVICE_TYPE = 0;
parameter SERDES_OR_DDR_N = 1;
parameter DATA_WIDTH = 16;
localparam DEVICE_6SERIES = 1;
localparam DEVICE_7SERIES = 0;
localparam DW = DATA_WIDTH - 1;
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16) (
// reset and clocks
input rst;
input clk;
input div_clk;
input loaden;
// data interface
input [DW:0] data_s0;
input [DW:0] data_s1;
input [DW:0] data_s2;
input [DW:0] data_s3;
input [DW:0] data_s4;
input [DW:0] data_s5;
input [DW:0] data_s6;
input [DW:0] data_s7;
output [DW:0] data_out_p;
output [DW:0] data_out_n;
input [(DATA_WIDTH-1):0] data_s0;
input [(DATA_WIDTH-1):0] data_s1;
input [(DATA_WIDTH-1):0] data_s2;
input [(DATA_WIDTH-1):0] data_s3;
input [(DATA_WIDTH-1):0] data_s4;
input [(DATA_WIDTH-1):0] data_s5;
input [(DATA_WIDTH-1):0] data_s6;
input [(DATA_WIDTH-1):0] data_s7;
output [(DATA_WIDTH-1):0] data_out_p;
output [(DATA_WIDTH-1):0] data_out_n;
// internal signals
wire [DW:0] data_out_s;
wire [DW:0] serdes_shift1_s;
wire [DW:0] serdes_shift2_s;
wire [(DATA_WIDTH-1):0] data_out_s;
wire [(DATA_WIDTH-1):0] serdes_shift1_s;
wire [(DATA_WIDTH-1):0] serdes_shift2_s;
// parameters
localparam DEVICE_6SERIES = 1;
localparam DEVICE_7SERIES = 0;
// instantiations
genvar l_inst;
generate
for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
if (SERDES_OR_DDR_N == 0) begin
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr (
.S (1'b0),
.CE (1'b1),
.R (rst),
.C (clk),
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
.Q (data_out_s[l_inst]));
end
if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin
if (DEVICE_TYPE == DEVICE_7SERIES) begin
OSERDESE2 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
@ -155,7 +121,7 @@ module ad_serdes_out (
.RST (rst));
end
if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin
if (DEVICE_TYPE == DEVICE_6SERIES) begin
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),