library- remove c5 cores
Rejeesh Kutty
parent
6c986d9b6a
commit
a27b30d380
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@ -1,67 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_cmos_out_core_c5 (
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// data interface
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input clk,
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input [ 1:0] din,
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output pad_out);
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// instantiations
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altddio_out #(
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.width (1),
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.lpm_hint ("UNUSED"))
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i_altddio_out (
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.outclock (clk),
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.datain_h (din[1]),
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.datain_l (din[0]),
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.dataout (pad_out),
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.outclocken (1'b1),
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.oe_out (),
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.oe (1'b1),
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.aclr (1'b0),
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.aset (1'b0),
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.sclr (1'b0),
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.sset (1'b0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -1,144 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
|
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// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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||||
// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_serdes_in_core_c5 #(
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parameter SERDES_FACTOR = 8) (
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input clk,
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input div_clk,
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input enable,
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input data_in,
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output [(SERDES_FACTOR-1):0] data);
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reg [(SERDES_FACTOR-1):0] data_int = 'd0;
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wire [(SERDES_FACTOR-1):0] data_s;
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assign data = data_int;
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always @(posedge div_clk) begin
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data_int <= data_s;
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end
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altlvds_rx i_altlvds_rx (
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.rx_enable (enable),
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.rx_in (data_in),
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.rx_inclock (clk),
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.rx_out (data_s),
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.dpa_pll_cal_busy (),
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.dpa_pll_recal (1'b0),
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.pll_areset (1'b0),
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.pll_phasecounterselect (),
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.pll_phasedone (1'b1),
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.pll_phasestep (),
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.pll_phaseupdown (),
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.pll_scanclk (),
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.rx_cda_max (),
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.rx_cda_reset (1'b0),
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.rx_channel_data_align (1'b0),
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.rx_coreclk (1'b1),
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.rx_data_align (1'b0),
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.rx_data_align_reset (1'b0),
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.rx_data_reset (1'b0),
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.rx_deskew (1'b0),
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.rx_divfwdclk (),
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.rx_dpa_lock_reset (1'b0),
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.rx_dpa_locked (),
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.rx_dpaclock (1'b0),
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.rx_dpll_enable (1'b1),
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.rx_dpll_hold (1'b0),
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.rx_dpll_reset (1'b0),
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.rx_fifo_reset (1'b0),
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.rx_locked (),
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.rx_outclock (),
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.rx_pll_enable (1'b1),
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.rx_readclock (1'b0),
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.rx_reset (1'b0),
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.rx_syncclock (1'b0));
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defparam
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i_altlvds_rx.buffer_implementation = "RAM",
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i_altlvds_rx.cds_mode = "UNUSED",
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i_altlvds_rx.common_rx_tx_pll = "OFF",
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i_altlvds_rx.data_align_rollover = 4,
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i_altlvds_rx.data_rate = "800.0 Mbps",
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i_altlvds_rx.deserialization_factor = SERDES_FACTOR,
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i_altlvds_rx.dpa_initial_phase_value = 0,
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i_altlvds_rx.dpll_lock_count = 0,
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i_altlvds_rx.dpll_lock_window = 0,
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i_altlvds_rx.enable_clock_pin_mode = "UNUSED",
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i_altlvds_rx.enable_dpa_align_to_rising_edge_only = "OFF",
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i_altlvds_rx.enable_dpa_calibration = "ON",
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i_altlvds_rx.enable_dpa_fifo = "UNUSED",
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i_altlvds_rx.enable_dpa_initial_phase_selection = "OFF",
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i_altlvds_rx.enable_dpa_mode = "OFF",
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i_altlvds_rx.enable_dpa_pll_calibration = "OFF",
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i_altlvds_rx.enable_soft_cdr_mode = "OFF",
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i_altlvds_rx.implement_in_les = "OFF",
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i_altlvds_rx.inclock_boost = 0,
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i_altlvds_rx.inclock_data_alignment = "EDGE_ALIGNED",
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i_altlvds_rx.inclock_period = 50000,
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i_altlvds_rx.inclock_phase_shift = 0,
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i_altlvds_rx.input_data_rate = 800,
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i_altlvds_rx.intended_device_family = "Cyclone V",
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i_altlvds_rx.lose_lock_on_one_change = "UNUSED",
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i_altlvds_rx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_in_core_c5",
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i_altlvds_rx.lpm_type = "altlvds_rx",
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i_altlvds_rx.number_of_channels = 1,
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i_altlvds_rx.outclock_resource = "Dual-Regional clock",
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i_altlvds_rx.pll_operation_mode = "NORMAL",
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i_altlvds_rx.pll_self_reset_on_loss_lock = "UNUSED",
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i_altlvds_rx.port_rx_channel_data_align = "PORT_UNUSED",
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i_altlvds_rx.port_rx_data_align = "PORT_UNUSED",
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i_altlvds_rx.refclk_frequency = "20.000000 MHz",
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i_altlvds_rx.registered_data_align_input = "UNUSED",
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i_altlvds_rx.registered_output = "OFF",
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i_altlvds_rx.reset_fifo_at_first_lock = "UNUSED",
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i_altlvds_rx.rx_align_data_reg = "RISING_EDGE",
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i_altlvds_rx.sim_dpa_is_negative_ppm_drift = "OFF",
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i_altlvds_rx.sim_dpa_net_ppm_variation = 0,
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i_altlvds_rx.sim_dpa_output_clock_phase_shift = 0,
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i_altlvds_rx.use_coreclock_input = "OFF",
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i_altlvds_rx.use_dpll_rawperror = "OFF",
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i_altlvds_rx.use_external_pll = "ON",
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i_altlvds_rx.use_no_phase_shift = "ON",
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i_altlvds_rx.x_on_bitslip = "ON",
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i_altlvds_rx.clk_src_is_pll = "off";
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -1,105 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_serdes_out_core_c5 #(
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parameter SERDES_FACTOR = 8) (
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input clk,
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input div_clk,
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input enable,
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output data_out,
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input [(SERDES_FACTOR-1):0] data);
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reg [(SERDES_FACTOR-1):0] data_int = 'd0;
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always @(posedge div_clk) begin
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data_int <= data;
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end
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altlvds_tx i_altlvds_tx (
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.tx_enable (enable),
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.tx_in (data),
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.tx_inclock (clk),
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.tx_out (data_out),
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.pll_areset (1'b0),
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.sync_inclock (1'b0),
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.tx_coreclock (),
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.tx_data_reset (1'b0),
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.tx_locked (),
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.tx_outclock (),
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.tx_pll_enable (1'b1),
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.tx_syncclock (1'b0));
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defparam
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i_altlvds_tx.center_align_msb = "UNUSED",
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i_altlvds_tx.common_rx_tx_pll = "OFF",
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i_altlvds_tx.coreclock_divide_by = 1,
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i_altlvds_tx.data_rate = "800.0 Mbps",
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i_altlvds_tx.deserialization_factor = SERDES_FACTOR,
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i_altlvds_tx.differential_drive = 0,
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i_altlvds_tx.enable_clock_pin_mode = "UNUSED",
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i_altlvds_tx.implement_in_les = "OFF",
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i_altlvds_tx.inclock_boost = 0,
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i_altlvds_tx.inclock_data_alignment = "EDGE_ALIGNED",
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i_altlvds_tx.inclock_period = 50000,
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i_altlvds_tx.inclock_phase_shift = 0,
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i_altlvds_tx.intended_device_family = "Cyclone V",
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i_altlvds_tx.lpm_hint = "CBX_MODULE_PREFIX=ad_serdes_out_core_c5",
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i_altlvds_tx.lpm_type = "altlvds_tx",
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i_altlvds_tx.multi_clock = "OFF",
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i_altlvds_tx.number_of_channels = 1,
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i_altlvds_tx.outclock_alignment = "EDGE_ALIGNED",
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i_altlvds_tx.outclock_divide_by = 1,
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i_altlvds_tx.outclock_duty_cycle = 50,
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i_altlvds_tx.outclock_multiply_by = 1,
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i_altlvds_tx.outclock_phase_shift = 0,
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i_altlvds_tx.outclock_resource = "Dual-Regional clock",
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i_altlvds_tx.output_data_rate = 800,
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i_altlvds_tx.pll_compensation_mode = "AUTO",
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i_altlvds_tx.pll_self_reset_on_loss_lock = "OFF",
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i_altlvds_tx.preemphasis_setting = 0,
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i_altlvds_tx.refclk_frequency = "20.000000 MHz",
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i_altlvds_tx.registered_input = "OFF",
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i_altlvds_tx.use_external_pll = "ON",
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i_altlvds_tx.use_no_phase_shift = "ON",
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i_altlvds_tx.vod_setting = 0,
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i_altlvds_tx.clk_src_is_pll = "off";
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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