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spi_engine: Fix indentation of axi_spi_engine.v

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Istvan Csomortani 2019-01-14 10:45:24 +00:00 committed by István Csomortáni
parent b81c8373e5
commit a19f6197cc
1 changed files with 348 additions and 354 deletions
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12
library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@ -237,8 +237,6 @@ generate if (MM_IF_TYPE == UP_FIFO) begin
end
endgenerate
// IRQ handling
reg [3:0] up_irq_mask = 'h0;
wire [3:0] up_irq_source;
@ -343,9 +341,8 @@ generate if (ASYNC_SPI_CLK) begin
wire spi_reset;
ad_rst i_spi_resetn (
.rst_async(up_sw_reset),
.preset(up_sw_reset),
.clk(spi_clk),
.rstn(),
.rst(spi_reset)
);
assign spi_resetn = ~spi_reset;
@ -380,8 +377,7 @@ util_axis_fifo #(
.m_axis_aresetn(spi_resetn),
.m_axis_ready(cmd_ready),
.m_axis_valid(cmd_valid),
.m_axis_data(cmd_data),
.m_axis_level()
.m_axis_data(cmd_data)
);
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
@ -406,8 +402,7 @@ util_axis_fifo #(
.m_axis_aresetn(spi_resetn),
.m_axis_ready(sdo_data_ready),
.m_axis_valid(sdo_data_valid),
.m_axis_data(sdo_data),
.m_axis_level()
.m_axis_data(sdo_data)
);
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
@ -426,7 +421,6 @@ util_axis_fifo #(
.s_axis_valid(sdi_data_valid),
.s_axis_data(sdi_data),
.s_axis_empty(),
.s_axis_room(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(sdi_fifo_out_ready),