axi_ad9361: Add parameter R1_MODE_EN
R1_MODE_EN can disable the second I/Q channel of the core. This way the user can save resources by cutting down the size of the core.main
Istvan Csomortani
parent
e42206e510
commit
a183e51a12
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@ -171,6 +171,7 @@ module axi_ad9361 (
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parameter DAC_DATAPATH_DISABLE = 0;
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parameter ADC_DATAPATH_DISABLE = 0;
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parameter TDD_CONTROL_EN = 0;
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parameter R1_MODE_EN = 0;
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// physical interface (receive-lvds)
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@ -602,7 +603,8 @@ module axi_ad9361 (
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axi_ad9361_rx #(
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.ID (ID),
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.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
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.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE),
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.R1_MODE_EN (R1_MODE_EN))
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i_rx (
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.mmcm_rst (mmcm_rst),
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.adc_rst (rst),
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@ -650,7 +652,8 @@ module axi_ad9361 (
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axi_ad9361_tx #(
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.ID (ID),
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.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
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.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE),
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.R1_MODE_EN (R1_MODE_EN))
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i_tx (
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.dac_clk (clk),
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.dac_valid (dac_valid_s),
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@ -103,6 +103,7 @@ module axi_ad9361_rx (
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parameter DATAPATH_DISABLE = 0;
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parameter ID = 0;
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parameter R1_MODE_EN = 0;
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// common
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@ -274,6 +275,9 @@ module axi_ad9361_rx (
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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generate
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if (R1_MODE_EN == 0) begin
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// channel 2 (i)
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axi_ad9361_rx_channel #(
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@ -340,6 +344,9 @@ module axi_ad9361_rx (
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.up_rdata (up_rdata_s[3]),
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.up_rack (up_rack_s[3]));
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end
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endgenerate
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// common processor control
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up_adc_common #(.ID (ID)) i_up_adc_common (
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@ -1,9 +1,9 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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//
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// All rights reserved.
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//
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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@ -21,16 +21,16 @@
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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@ -47,7 +47,7 @@ module axi_ad9361_tx (
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dac_clksel,
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dac_r1_mode,
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adc_data,
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// delay interface
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up_dld,
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@ -101,6 +101,7 @@ module axi_ad9361_tx (
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parameter DATAPATH_DISABLE = 0;
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parameter ID = 0;
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parameter R1_MODE_EN = 0;
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// dac interface
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@ -110,7 +111,7 @@ module axi_ad9361_tx (
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output dac_clksel;
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output dac_r1_mode;
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input [47:0] adc_data;
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// delay interface
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output [15:0] up_dld;
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@ -233,7 +234,7 @@ module axi_ad9361_tx (
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end
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// dac channel
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axi_ad9361_tx_channel #(
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.CHANNEL_ID (0),
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.Q_OR_I_N (0),
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@ -262,7 +263,7 @@ module axi_ad9361_tx (
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.up_rack (up_rack_s[0]));
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// dac channel
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axi_ad9361_tx_channel #(
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.CHANNEL_ID (1),
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.Q_OR_I_N (1),
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@ -290,8 +291,11 @@ module axi_ad9361_tx (
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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generate
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if (R1_MODE_EN == 0) begin
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// dac channel
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axi_ad9361_tx_channel #(
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.CHANNEL_ID (2),
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.Q_OR_I_N (0),
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@ -320,7 +324,7 @@ module axi_ad9361_tx (
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.up_rack (up_rack_s[2]));
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// dac channel
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axi_ad9361_tx_channel #(
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.CHANNEL_ID (3),
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.Q_OR_I_N (1),
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@ -348,6 +352,9 @@ module axi_ad9361_tx (
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.up_rdata (up_rdata_s[3]),
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.up_rack (up_rack_s[3]));
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end
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endgenerate
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// dac common processor interface
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up_dac_common #(.ID (ID)) i_up_dac_common (
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@ -387,7 +394,7 @@ module axi_ad9361_tx (
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.up_raddr (up_raddr),
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.up_rdata (up_rdata_s[4]),
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.up_rack (up_rack_s[4]));
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// dac delay control
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up_delay_cntrl #(.DATA_WIDTH(16), .BASE_ADDRESS(6'h12)) i_delay_cntrl (
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