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util_axis_fifo: Improve clock gating of registers and BRAM 

Currently the BRAM and data registers in the util_axis_data are ungated
when the FIFO is ready to receive data. This good for high-performance
since it reduces the number of control signals. But it is bad from a power
point of view since it causes additional reads and writes.

Change the core gate the BRAM and data register if either the consumer is
not ready to accept data or the producer has no data to offer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-03-27 16:56:46 +02:00
parent 72cdd846b0
commit a0e30a2211
1 changed files with 3 additions and 3 deletions
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6
library/util_axis_fifo/util_axis_fifo.v
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@ -94,7 +94,7 @@ assign s_axis_empty = s_axis_ready;
assign s_axis_room = s_axis_ready;
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
cdc_sync_fifo_ram <= s_axis_data;
end
@ -171,7 +171,7 @@ fifo_address_sync #(
end
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
ram[s_axis_waddr] <= s_axis_data;
end
@ -192,7 +192,7 @@ always @(posedge m_axis_aclk) begin
end
always @(posedge m_axis_aclk) begin
if (~valid || m_axis_ready)
if ((~valid || m_axis_ready) && _m_axis_valid)
data <= ram[m_axis_raddr];
end