diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index 342443f6b..1aadad2b6 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -46,6 +46,8 @@ module util_adxcvr #( parameter integer QPLL_REFCLK_DIV = 1, parameter integer QPLL_FBDIV_RATIO = 1, + parameter [15:0] POR_CFG = 16'b0000000000000110, + parameter [15:0] PPF0_CFG = 16'b0000011000000000, parameter [26:0] QPLL_CFG = 27'h0680181, parameter [ 9:0] QPLL_FBDIV = 10'b0000110000, parameter [15:0] QPLL_CFG0 = 16'b0011001100011100, @@ -55,6 +57,9 @@ module util_adxcvr #( parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000, parameter [15:0] QPLL_CFG3 = 16'b0000000100100000, parameter [15:0] QPLL_CFG4 = 16'b0000000000000011, + parameter [15:0] QPLL_CP_G3 = 10'b0000011111, + parameter [15:0] QPLL_LPF = 10'b0100110111, + parameter [15:0] QPLL_CP = 10'b0001111111, parameter [15:0] GTY4_PPF0_CFG = 16'b0000100000000000, // cpll-configuration @@ -76,6 +81,9 @@ module util_adxcvr #( parameter integer TX_OUT_DIV = 1, parameter integer TX_CLK25_DIV = 20, parameter integer TX_LANE_INVERT = 0, + parameter [15:0] TX_PI_BIASSET = 1, + parameter [15:0] TXPI_CFG = 16'b0000000001010100, + parameter [15:0] A_TXDIFFCTRL = 5'b10110, // rx-configuration @@ -1127,6 +1135,8 @@ module util_adxcvr #( .XCVR_TYPE (XCVR_TYPE), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV), .QPLL_CFG0 (QPLL_CFG0), @@ -1135,6 +1145,9 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), .QPLL_CFG4 (QPLL_CFG4), .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_0 ( @@ -1180,6 +1193,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 0) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -1290,6 +1306,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 1) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -1400,6 +1419,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 2) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -1510,6 +1532,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 3) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -1612,6 +1637,8 @@ module util_adxcvr #( .XCVR_TYPE (XCVR_TYPE), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV), .QPLL_CFG0 (QPLL_CFG0), @@ -1620,6 +1647,9 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), .QPLL_CFG4 (QPLL_CFG4), .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_4 ( @@ -1665,6 +1695,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 4) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -1775,6 +1808,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 5) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -1885,6 +1921,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 6) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -1995,6 +2034,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 7) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2097,6 +2139,8 @@ module util_adxcvr #( .XCVR_TYPE (XCVR_TYPE), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV), .QPLL_CFG0 (QPLL_CFG0), @@ -2105,6 +2149,9 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), .QPLL_CFG4 (QPLL_CFG4), .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_8 ( @@ -2150,6 +2197,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 8) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2260,6 +2310,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 9) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2370,6 +2423,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 10) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2480,6 +2536,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 11) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2582,6 +2641,8 @@ module util_adxcvr #( .XCVR_TYPE (XCVR_TYPE), .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), .QPLL_CFG (QPLL_CFG), .QPLL_FBDIV (QPLL_FBDIV), .QPLL_CFG0 (QPLL_CFG0), @@ -2590,6 +2651,9 @@ module util_adxcvr #( .QPLL_CFG2 (QPLL_CFG2), .QPLL_CFG2_G3 (QPLL_CFG2_G3), .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), .QPLL_CFG4 (QPLL_CFG4), .GTY4_PPF0_CFG (GTY4_PPF0_CFG)) i_xcm_12 ( @@ -2635,6 +2699,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 12) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2745,6 +2812,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 13) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2855,6 +2925,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 14) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), @@ -2965,6 +3038,9 @@ module util_adxcvr #( .TX_OUT_DIV (TX_OUT_DIV), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_POLARITY ((TX_LANE_INVERT >> 15) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .RX_OUT_DIV (RX_OUT_DIV), .RX_CLK25_DIV (RX_CLK25_DIV), .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index c99d467b3..cea989fd9 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -56,6 +56,9 @@ module util_adxcvr_xch #( parameter integer TX_OUT_DIV = 1, parameter integer TX_CLK25_DIV = 20, parameter integer TX_POLARITY = 0, + parameter [15:0] TX_PI_BIASSET = 1, + parameter [15:0] TXPI_CFG = 16'b0000000001010100, + parameter [15:0] A_TXDIFFCTRL = 5'b10110, parameter integer RX_OUT_DIV = 1, parameter integer RX_CLK25_DIV = 20, @@ -1565,7 +1568,7 @@ module util_adxcvr_xch #( .A_RXOSCALRESET (1'b0), .A_RXPROGDIVRESET (1'b0), .A_RXTERMINATION (1'b1), - .A_TXDIFFCTRL (5'b10110), + .A_TXDIFFCTRL (A_TXDIFFCTRL), .A_TXPROGDIVRESET (1'b0), .CAPBYPASS_FORCE (1'b0), .CBCC_DATA_SOURCE_SEL ("DECODED"), @@ -1949,7 +1952,7 @@ module util_adxcvr_xch #( .TXPH_CFG (16'b0000001100100011), .TXPH_CFG2 (16'b0000000000000000), .TXPH_MONITOR_SEL (5'b00000), - .TXPI_CFG (16'b0000000001010100), + .TXPI_CFG (TXPI_CFG), .TXPI_CFG0 (2'b00), .TXPI_CFG1 (2'b00), .TXPI_CFG2 (2'b00), @@ -2001,7 +2004,7 @@ module util_adxcvr_xch #( .TX_PHICAL_CFG0 (16'b0000000000000000), .TX_PHICAL_CFG1 (16'b0111111000000000), .TX_PHICAL_CFG2 (16'b0000001000000001), - .TX_PI_BIASSET (1), + .TX_PI_BIASSET (TX_PI_BIASSET), .TX_PI_IBIAS_MID (2'b00), .TX_PMADATA_OPT (1'b0), .TX_PMA_POWER_SAVE (1'b0), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v index a4fe5cd5d..56dca880a 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -42,6 +42,8 @@ module util_adxcvr_xcm #( parameter integer XCVR_TYPE = 0, parameter integer QPLL_REFCLK_DIV = 1, parameter integer QPLL_FBDIV_RATIO = 1, + parameter [15:0] POR_CFG = 16'b0000000000000110, + parameter [15:0] PPF0_CFG = 16'b0000011000000000, parameter [26:0] QPLL_CFG = 27'h0680181, parameter [ 9:0] QPLL_FBDIV = 10'b0000110000, parameter [15:0] QPLL_CFG0 = 16'b0011001100011100, @@ -51,8 +53,11 @@ module util_adxcvr_xcm #( parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000, parameter [15:0] QPLL_CFG3 = 16'b0000000100100000, parameter [15:0] QPLL_CFG4 = 16'b0000000000000011, - + parameter [15:0] QPLL_CP_G3 = 10'b0000011111, + parameter [15:0] QPLL_LPF = 10'b0100110111, + parameter [15:0] QPLL_CP = 10'b0001111111, parameter [15:0] GTY4_PPF0_CFG = 16'b0000100000000000 + ) ( // reset and clocks @@ -376,8 +381,8 @@ module util_adxcvr_xcm #( .BIAS_CFG_RSVD (16'b0000000000000000), .COMMON_CFG0 (16'b0000000000000000), .COMMON_CFG1 (16'b0000000000000000), - .POR_CFG (16'b0000000000000110), - .PPF0_CFG (16'b0000011000000000), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), .PPF1_CFG (16'b0000011000000000), .QPLL0CLKOUT_RATE ("HALF"), .QPLL0_CFG0 (QPLL_CFG0), @@ -387,15 +392,15 @@ module util_adxcvr_xcm #( .QPLL0_CFG2_G3 (QPLL_CFG2_G3), .QPLL0_CFG3 (QPLL_CFG3), .QPLL0_CFG4 (QPLL_CFG4), - .QPLL0_CP (10'b0001111111), - .QPLL0_CP_G3 (10'b0000011111), + .QPLL0_CP (QPLL_CP), + .QPLL0_CP_G3 (QPLL_CP_G3), .QPLL0_FBDIV (QPLL_FBDIV), .QPLL0_FBDIV_G3 (160), .QPLL0_INIT_CFG0 (16'b0000001010110010), .QPLL0_INIT_CFG1 (8'b00000000), .QPLL0_LOCK_CFG (16'b0010010111101000), .QPLL0_LOCK_CFG_G3 (16'b0010010111101000), - .QPLL0_LPF (10'b0100110111), + .QPLL0_LPF (QPLL_LPF), .QPLL0_LPF_G3 (10'b0111010101), .QPLL0_PCI_EN (1'b0), .QPLL0_RATE_SW_USE_DRP (1'b1),