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usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints

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Adrian Costina 2014-10-22 13:20:44 +03:00
parent cd9033296c
commit a0d27a117c
2 changed files with 32 additions and 40 deletions
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4
projects/usdrx1/common/usdrx1_bd.tcl
View File

@ -198,6 +198,10 @@ connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_3/adc_raddr_in]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_0/adc_sync_out]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_1/adc_sync_in]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_2/adc_sync_in]
connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_3/adc_sync_in]
# interconnect (cpu)

12
projects/usdrx1/zc706/system_constr.xdc
View File

@ -83,15 +83,3 @@ set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data
create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]