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axi_dacfifo: Add gray coder/decoder module 

Use gray coder/decoder modules, instead of functions.
This way it can be used paramterized data width on the
coders/decoders.
main
Istvan Csomortani 2017-07-06 09:47:26 +01:00
parent 866d79dee2
commit a0b33898d2
3 changed files with 89 additions and 93 deletions
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108
library/xilinx/axi_dacfifo/axi_dacfifo_dac.v
View File

@ -109,54 +109,20 @@ module axi_dacfifo_dac #(
// internal signals
wire [AXI_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;
wire [(AXI_ADDRESS_WIDTH-1):0] axi_mem_raddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_laddr_s;
wire [AXI_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;
wire [(AXI_ADDRESS_WIDTH-1):0] axi_mem_raddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_laddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_waddr_b2g_s;
wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_laddr_b2g_s;
wire [(DAC_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2_g2b_s;
wire [DAC_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;
wire dac_xfer_init_s;
wire dac_last_axi_beats_s;
// binary to grey conversion
function [9:0] b2g;
input [9:0] b;
reg [9:0] g;
begin
g[9] = b[9];
g[8] = b[9] ^ b[8];
g[7] = b[8] ^ b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [9:0] g2b;
input [9:0] g;
reg [9:0] b;
begin
b[9] = g[9];
b[8] = b[9] ^ g[8];
b[7] = b[8] ^ g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
wire [DAC_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;
wire dac_xfer_init_s;
wire dac_last_axi_beats_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_laddr_m2_g2b_s;
// write interface
@ -170,11 +136,23 @@ module axi_dacfifo_dac #(
axi_mem_waddr <= axi_mem_waddr + 1'b1;
axi_mem_laddr <= (axi_dlast == 1'b1) ? axi_mem_waddr : axi_mem_laddr;
end
axi_mem_waddr_g <= b2g(axi_mem_waddr_s);
axi_mem_laddr_g <= b2g(axi_mem_laddr_s);
axi_mem_waddr_g <= axi_mem_waddr_b2g_s;
axi_mem_laddr_g <= axi_mem_laddr_b2g_s;
end
end
ad_b2g # (
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_axi_mem_waddr_b2g (
.din (axi_mem_waddr_s),
.dout (axi_mem_waddr_b2g_s));
ad_b2g # (
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_axi_mem_laddr_b2g (
.din (axi_mem_laddr_s),
.dout (axi_mem_laddr_b2g_s));
// scale the axi_mem_* addresses
assign axi_mem_raddr_s = (MEM_RATIO == 1) ? axi_mem_raddr :
@ -204,7 +182,7 @@ module axi_dacfifo_dac #(
end else begin
axi_mem_raddr_m1 <= dac_mem_raddr_g;
axi_mem_raddr_m2 <= axi_mem_raddr_m1;
axi_mem_raddr <= g2b(axi_mem_raddr_m2);
axi_mem_raddr <= axi_mem_raddr_m2_g2b_s;
axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_ADDRESS_WIDTH-1:0];
if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin
axi_dready <= 1'b0;
@ -214,6 +192,12 @@ module axi_dacfifo_dac #(
end
end
ad_g2b #(
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_axi_mem_raddr_m2_g2b (
.din (axi_mem_raddr_m2),
.dout (axi_mem_raddr_m2_g2b_s));
// CDC for xfer_req signal
always @(posedge dac_clk) begin
@ -262,16 +246,28 @@ module axi_dacfifo_dac #(
end else begin
dac_mem_waddr_m1 <= axi_mem_waddr_g;
dac_mem_waddr_m2 <= dac_mem_waddr_m1;
dac_mem_waddr <= g2b(dac_mem_waddr_m2);
dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
dac_mem_laddr_m1 <= axi_mem_laddr_g;
dac_mem_laddr_m2 <= dac_mem_laddr_m1;
dac_mem_laddr <= g2b(dac_mem_laddr_m2);
dac_mem_laddr <= dac_mem_laddr_m2_g2b_s;
dac_dlast_m1 <= axi_dlast;
dac_dlast_m2 <= dac_dlast_m1;
dac_dlast <= dac_dlast_m2;
end
end
ad_g2b #(
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_dac_mem_waddr_m2_g2b (
.din (dac_mem_waddr_m2),
.dout (dac_mem_waddr_m2_g2b_s));
ad_g2b #(
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_dac_mem_laddr_m2_g2b (
.din (dac_mem_laddr_m2),
.dout (dac_mem_laddr_m2_g2b_s));
assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr;
always @(posedge dac_clk) begin
dac_mem_valid <= (dac_mem_enable) ? dac_valid : 1'b0;
@ -312,10 +308,16 @@ module axi_dacfifo_dac #(
((dac_last_beats > 1'b1) && (dac_last_axi_beats_s > 1'b0) && (dac_beat_cnt == dac_last_beats-1))) ? 0 : dac_beat_cnt + 1;
dac_mem_raddr <= ((dac_last_axi_beats_s) && (dac_beat_cnt == dac_last_beats-1)) ? (dac_mem_laddr + MEM_RATIO) : dac_mem_raddr + 1'b1;
end
dac_mem_raddr_g <= b2g(dac_mem_raddr);
dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
end
end
ad_b2g # (
.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
) i_dac_mem_raddr_b2g (
.din (dac_mem_raddr),
.dout (dac_mem_raddr_b2g_s));
// underflow generation, there is no overflow
always @(posedge dac_clk) begin

2
library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
View File

@ -6,6 +6,8 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_dacfifo
adi_ip_files axi_dacfifo [list \
"$ad_hdl_dir/library/common/ad_g2b.v" \
"$ad_hdl_dir/library/common/ad_b2g.v" \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"$ad_hdl_dir/library/common/util_dacfifo_bypass.v" \

72
library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
View File

@ -155,52 +155,20 @@ module axi_dacfifo_wr #(
wire dma_xfer_init;
wire dma_mem_wea_s;
wire dma_rst_s;
wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s;
wire [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
wire [AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;
wire [(AXI_DATA_WIDTH-1):0] axi_mem_rdata_s;
wire axi_mem_rvalid_s;
wire axi_mem_last_s;
wire [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2_g2b_s;
wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_b2g_s;
wire axi_waddr_ready_s;
wire axi_wready_s;
// binary to grey conversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// Instantiations
// An asymmetric memory to transfer data from DMAC interface to AXI Memory Map
@ -290,10 +258,16 @@ module axi_dacfifo_wr #(
if (dma_mem_last_read_s == 1'b1) begin
dma_mem_waddr <= 'h0;
end
dma_mem_waddr_g <= b2g(dma_mem_waddr);
dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
end
end
ad_b2g # (
.DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
) i_dma_mem_waddr_b2g (
.din (dma_mem_waddr),
.dout (dma_mem_waddr_b2g_s));
// The memory module request data until reaches the high threshold.
always @(posedge dma_clk) begin
@ -306,7 +280,7 @@ module axi_dacfifo_wr #(
end else begin
dma_mem_raddr_m1 <= axi_mem_raddr_g;
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
dma_mem_raddr <= g2b(dma_mem_raddr_m2);
dma_mem_raddr <= dma_mem_raddr_m2_g2b_s;
dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0];
if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
dma_ready_out <= 1'b0;
@ -316,6 +290,12 @@ module axi_dacfifo_wr #(
end
end
ad_g2b # (
.DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH)
) i_dma_mem_raddr_g2b (
.din (dma_mem_raddr_m2),
.dout (dma_mem_raddr_m2_g2b_s));
// Read address generation for the asymmetric memory
// CDC for the memory write address, xfer_req and xfer_last
@ -334,10 +314,16 @@ module axi_dacfifo_wr #(
axi_xfer_init = ~axi_xfer_req_m[2] & axi_xfer_req_m[1];
axi_mem_waddr_m1 <= dma_mem_waddr_g;
axi_mem_waddr_m2 <= axi_mem_waddr_m1;
axi_mem_waddr <= g2b(axi_mem_waddr_m2);
axi_mem_waddr <= axi_mem_waddr_m2_g2b_s;
end
end
ad_g2b # (
.DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH)
) i_axi_mem_waddr_g2b (
.din (axi_mem_waddr_m2),
.dout (axi_mem_waddr_m2_g2b_s));
// check if the AXI write channel is ready
assign axi_wready_s = ~axi_wvalid | axi_wready;
@ -422,10 +408,16 @@ module axi_dacfifo_wr #(
axi_mem_raddr <= 'b0;
axi_mem_last_read_toggle <= ~axi_mem_last_read_toggle;
end
axi_mem_raddr_g <= b2g(axi_mem_raddr);
axi_mem_raddr_g <= axi_mem_raddr_b2g_s;
end
end
ad_b2g # (
.DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH)
) i_axi_mem_raddr_b2g (
.din (axi_mem_raddr),
.dout (axi_mem_raddr_b2g_s));
// AXI Memory Map interface write address channel
assign axi_awid = 4'b0000;