diff --git a/library/Makefile b/library/Makefile index 7b7b4e429..33c7090d0 100644 --- a/library/Makefile +++ b/library/Makefile @@ -11,7 +11,6 @@ all: lib clean: make -C axi_ad6676 clean - make -C axi_ad7175 clean make -C axi_ad9122 clean make -C axi_ad9144 clean make -C axi_ad9152 clean @@ -71,7 +70,6 @@ clean-all:clean lib: -make -C axi_ad6676 - -make -C axi_ad7175 -make -C axi_ad9122 -make -C axi_ad9144 -make -C axi_ad9152 diff --git a/library/axi_ad7175/Makefile b/library/axi_ad7175/Makefile deleted file mode 100644 index 3b09f223b..000000000 --- a/library/axi_ad7175/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -#################################################################################### -#################################################################################### -## Copyright 2011(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### -#################################################################################### - -M_DEPS := axi_ad7175_ip.tcl -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/up_axi.v -M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_drp_cntrl.v -M_DEPS += ../common/up_xfer_cntrl.v -M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += up_adc_common.v -M_DEPS += ad_datafmt.v -M_DEPS += ad7175_if.v -M_DEPS += axi_ad7175.v -M_DEPS += axi_ad7175_channel.v -M_DEPS += clk_div.v - -M_VIVADO := vivado -mode batch -source - -M_FLIST := *.cache -M_FLIST += *.data -M_FLIST += *.xpr -M_FLIST += *.log -M_FLIST += component.xml -M_FLIST += *.jou -M_FLIST += xgui -M_FLIST += .Xil - - - -.PHONY: all clean clean-all -all: axi_ad7175.xpr - - -clean:clean-all - - -clean-all: - rm -rf $(M_FLIST) - - -axi_ad7175.xpr: $(M_DEPS) - rm -rf $(M_FLIST) - $(M_VIVADO) axi_ad7175_ip.tcl >> axi_ad7175_ip.log 2>&1 - -#################################################################################### -#################################################################################### diff --git a/library/axi_ad7175/ad7175_if.v b/library/axi_ad7175/ad7175_if.v deleted file mode 100644 index 0d2917e68..000000000 --- a/library/axi_ad7175/ad7175_if.v +++ /dev/null @@ -1,423 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -//------------------------------------------------------------------------------ -//----------- Module Declaration ----------------------------------------------- -//------------------------------------------------------------------------------ -module ad7175_if - ( - // Clock and Reset signals - input fpga_clk_i, - input adc_clk_i, - input reset_n_i, - - // Conversion control signals - input start_conversion_i, - output [31:0] dma_data_o, - output dma_data_rdy_o, - - // Transmit data on request signals - input start_transmission_i, - input [31:0] tx_data_i, - output tx_data_rdy_o, - - // Read data on request signals - input start_read_i, - output [31:0] rx_data_o, - output rx_data_rdy_o, - - // AD7175 IC control signals - input adc_sdo_i, - output adc_sdi_o, - output adc_cs_o, - output adc_sclk_o, - - // ADC status - output reg adc_status_o - ); - -//------------------------------------------------------------------------------ -//----------- Registers Declarations ------------------------------------------- -//------------------------------------------------------------------------------ -// State Machine Registers -reg [10:0] present_state; // Present FSM State -reg [10:0] next_state; // Next FSM State -reg [10:0] present_state_m1; // Used to synchronise FSM States between different clock domains - -// SCLK Registers -reg [7:0] sclk_cnt; // Used to count SCLK Ticks -reg [7:0] sclk_demand; // Used to set number of SCLK Ticks - -// Transmit Data Registers -reg [47:0] tx_data_reg; // Used to shift data out -reg [47:0] tx_data_reg_switch; // Used to select data that is being sent -reg tx_data_rdy_int; // Used to signal the end of a transmit cycle - -// Receive Data Registers -reg [47:0] rx_data_reg; // Used to shift data in -reg [31:0] rx_read_data_reg; // Used to store read data -reg rx_data_rdy_int; // Used to signal the end of a read cycle - -// Conversion Data Registers -reg [31:0] dma_rx_data_reg; // Used to store conversion result (STATUS_REG[31:24] + DATA_REG[23:0]) -reg dma_rdy_int; // Used to signal the end of a conversion read - -// Internal registers used for external ports -reg adc_sdi_o_int; // Used for adc_sdi_o -reg cs_int; // Used for adc_cs_o - -//------------------------------------------------------------------------------ -//----------- Wires Declarations ----------------------------------------------- -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -//----------- Local Parameters ------------------------------------------------- -//------------------------------------------------------------------------------ -// ADC Controller State Machine States -parameter ADC_IDLE_STATE = 11'b00000000001; // Waits for Start Conversion / Start Transmission / Start Read -parameter ADC_WAIT_FOR_DATA_STATE = 11'b00000000010; // Waits for adc_sdo_i to go low (signals new data is available) -parameter ADC_PREP_READ_RESULT_STATE = 11'b00000000100; // Prepares data to perform Status + Data Register Read -parameter ADC_READ_RESULT_STATE = 11'b00000001000; // Reads Status + Data Register -parameter ADC_READ_RESULT_DONE_STATE = 11'b00000010000; // Signals completion of Status + Data Register Read -parameter ADC_PREP_SEND_DATA_STATE = 11'b00000100000; // Prepares data to perform Data Transmit -parameter ADC_SEND_DATA_STATE = 11'b00001000000; // Transmit Data -parameter ADC_SEND_DATA_DONE_STATE = 11'b00010000000; // Signals completion of Data Transmission -parameter ADC_PREP_READ_DATA_STATE = 11'b00100000000; // Prepares data to perform Data Read -parameter ADC_READ_DATA_STATE = 11'b01000000000; // Reads Data -parameter ADC_READ_DATA_DONE_STATE = 11'b10000000000; // Signals completion of Data Read - -// Number of SCLK Periods required for Status + Data Read -parameter ADC_SCLK_PERIODS = 8'd48; - -//------------------------------------------------------------------------------ -//----------- Assign/Always Blocks --------------------------------------------- -//------------------------------------------------------------------------------ -assign adc_sdi_o = adc_sdi_o_int; -assign adc_sclk_o = (((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))&&(sclk_cnt != 8'd0)) ? adc_clk_i : 1'b1; -assign dma_data_o = dma_rx_data_reg; -assign dma_data_rdy_o = dma_rdy_int; -assign adc_cs_o = cs_int; -assign tx_data_rdy_o = tx_data_rdy_int; -assign rx_data_o = rx_read_data_reg; -assign rx_data_rdy_o = rx_data_rdy_int; - -// Register States -always @(posedge fpga_clk_i) -begin - if(reset_n_i == 1'b0) - begin - present_state <= ADC_IDLE_STATE; - adc_status_o <= 1'b0; - end - else - begin - present_state <= next_state; - adc_status_o <= 1'b1; - end -end - -// State switch logic -always @(posedge fpga_clk_i) -begin - next_state <= present_state; - case(present_state) - ADC_IDLE_STATE: - begin - // If transmit data is required - if(start_transmission_i == 1'b1) - begin - next_state <= ADC_PREP_SEND_DATA_STATE; - end - // If read data is required - else if(start_read_i == 1'b1) - begin - next_state <= ADC_PREP_READ_DATA_STATE; - end - // If start conversion has been requested - else if(start_conversion_i == 1'b1) - begin - next_state <= ADC_WAIT_FOR_DATA_STATE; - end - end - ADC_WAIT_FOR_DATA_STATE: - begin - // If new data is available - if(adc_sdo_i == 1'b0) - begin - next_state <= ADC_PREP_READ_RESULT_STATE; - end - // If transmit data is required - else if(start_transmission_i == 1'b1) - begin - next_state <= ADC_PREP_SEND_DATA_STATE; - end - // If read data is required - else if(start_read_i == 1'b1) - begin - next_state <= ADC_PREP_READ_DATA_STATE; - end - // If transmit data is not required anymore - else if(start_conversion_i == 1'b0) - begin - next_state <= ADC_IDLE_STATE; - end - end - ADC_PREP_READ_RESULT_STATE: - begin - if(present_state_m1 == ADC_PREP_READ_RESULT_STATE) - begin - next_state <= ADC_READ_RESULT_STATE; - end - end - ADC_READ_RESULT_STATE: - begin - // If data has been sent - if(sclk_cnt == 8'd0) - begin - next_state <= ADC_READ_RESULT_DONE_STATE; - end - end - ADC_READ_RESULT_DONE_STATE: - begin - next_state <= ADC_IDLE_STATE; - end - ADC_PREP_SEND_DATA_STATE: - begin - if(present_state_m1 == ADC_PREP_SEND_DATA_STATE) - begin - next_state <= ADC_SEND_DATA_STATE; - end - end - ADC_SEND_DATA_STATE: - begin - // If data has been sent - if(sclk_cnt == 8'd0) - begin - next_state <= ADC_SEND_DATA_DONE_STATE; - end - end - ADC_SEND_DATA_DONE_STATE: - begin - next_state <= ADC_IDLE_STATE; - end - ADC_PREP_READ_DATA_STATE: - begin - if(present_state_m1 == ADC_PREP_READ_DATA_STATE) - begin - next_state <= ADC_READ_DATA_STATE; - end - end - ADC_READ_DATA_STATE: - begin - // If data has been sent - if(sclk_cnt == 8'd0) - begin - next_state <= ADC_READ_DATA_DONE_STATE; - end - end - ADC_READ_DATA_DONE_STATE: - begin - next_state <= ADC_IDLE_STATE; - end - default: - begin - next_state <= ADC_IDLE_STATE; - end - endcase -end - -// State output logic -always @(posedge fpga_clk_i) -begin - if(reset_n_i == 1'b0) - begin - dma_rdy_int <= 1'b0; - cs_int <= 1'b1; - tx_data_rdy_int <= 1'b0; - rx_data_rdy_int <= 1'b0; - end - else - begin - case(present_state) - ADC_IDLE_STATE: - begin - dma_rdy_int <= 1'b0; - tx_data_rdy_int <= 1'b0; - rx_data_rdy_int <= 1'b0; - cs_int <= 1'b1; - end - ADC_WAIT_FOR_DATA_STATE: - begin - cs_int <= 1'b0; - end - ADC_PREP_READ_RESULT_STATE: - begin - dma_rdy_int <= 1'b0; - tx_data_reg_switch <= 48'h400044000000; - cs_int <= 1'b0; - end - ADC_READ_RESULT_STATE: - begin - dma_rdy_int <= 1'b0; - cs_int <= 1'b0; - end - ADC_READ_RESULT_DONE_STATE: - begin - // Final data = Status Reg + Data Reg - dma_rx_data_reg <= {rx_data_reg[39:32], rx_data_reg[23:0]}; - dma_rdy_int <= 1'b1; - cs_int <= 1'b1; - end - ADC_PREP_SEND_DATA_STATE: - begin - // Maximum 32 bits transmission (that is why I add 16'd0 to the LSB) - tx_data_rdy_int <= 1'b1; - cs_int <= 1'b1; - tx_data_reg_switch <= {tx_data_i, 16'd0}; - end - ADC_SEND_DATA_STATE: - begin - tx_data_rdy_int <= 1'b0; - cs_int <= 1'b0; - end - ADC_SEND_DATA_DONE_STATE: - begin - tx_data_rdy_int <= 1'b1; - cs_int <= 1'b1; - end - ADC_PREP_READ_DATA_STATE: - begin - // Maximum 32 bits transmission (that is why I add 16'd0 to the LSB) - cs_int <= 1'b1; - rx_data_rdy_int <= 1'b1; - tx_data_reg_switch <= {2'b01, tx_data_i[29:0], 16'd0}; - end - ADC_READ_DATA_STATE: - begin - cs_int <= 1'b0; - rx_data_rdy_int <= 1'b0; - end - ADC_READ_DATA_DONE_STATE: - begin - rx_read_data_reg <= rx_data_reg[31:0]; - cs_int <= 1'b1; - rx_data_rdy_int <= 1'b1; - end - default: - begin - tx_data_rdy_int <= 1'b0; - rx_data_rdy_int <= 1'b0; - dma_rdy_int <= 1'b0; - cs_int <= 1'b1; - end - endcase - end -end - -// Synchronise States between different clock domains -always @(posedge adc_clk_i) -begin - present_state_m1 <= present_state; -end - -// Select size of transfered data according to desired registers (see AD7176_2 Datasheet for details) -always @(posedge fpga_clk_i) -begin - case(tx_data_i[29:24]) - 6'h00: - begin - sclk_demand <= 8'd16; - end - 6'h01, 6'h02, 6'h06, 6'h07, 6'h10, 6'h11, 6'h12, 6'h13, 6'h20, 6'h21, 6'h22, 6'h23, 6'h28, 6'h29, 6'h2a, 6'h2b: - begin - sclk_demand <= 8'd24; - end - 6'h03, 6'h04, 6'h30, 6'h31, 6'h32, 6'h33, 6'h38, 6'h39, 6'h3a, 6'h3b: - begin - sclk_demand <= 8'd32; - end - default: - begin - sclk_demand <= 8'd16; - end - endcase -end - -// Serial Data In -always @(posedge adc_clk_i) -begin - if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE)) - begin - sclk_cnt <= sclk_cnt - 8'd1; - rx_data_reg <= {rx_data_reg[46:0], adc_sdo_i}; - end - else - begin - if((present_state_m1 == ADC_PREP_SEND_DATA_STATE)||(present_state_m1 == ADC_PREP_READ_DATA_STATE)) - begin - sclk_cnt <= sclk_demand; - end - else - begin - sclk_cnt <= ADC_SCLK_PERIODS; - end - if(present_state_m1 == ADC_IDLE_STATE) - begin - rx_data_reg <= 48'd0; - end - end -end - -// Serial Data Out -always @(negedge adc_clk_i) -begin - if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE)) - begin - adc_sdi_o_int <= tx_data_reg[47]; - tx_data_reg <= {tx_data_reg[46:0], 1'b0}; - end - else - begin - tx_data_reg <= tx_data_reg_switch; - end -end - -endmodule diff --git a/library/axi_ad7175/ad_datafmt.v b/library/axi_ad7175/ad_datafmt.v deleted file mode 100644 index 8a356085c..000000000 --- a/library/axi_ad7175/ad_datafmt.v +++ /dev/null @@ -1,117 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// data format (offset binary or 2's complement only) - -`timescale 1ps/1ps - -module ad_datafmt ( - - // data path - - clk, - valid, - data, - valid_out, - data_out, - - // control signals - - dfmt_enable, - dfmt_type, - dfmt_se); - - // delayed data bus width - - parameter DATA_WIDTH = 16; - parameter DATA_WIDTH_OUT = 16; - localparam DW = DATA_WIDTH - 1; - localparam DW1 = DATA_WIDTH_OUT - 1; - - // data path - - input clk; - input valid; - input [ DW:0] data; - output valid_out; - output [DW1:0] data_out; - - // control signals - - input dfmt_enable; - input dfmt_type; - input dfmt_se; - - // internal registers - - reg valid_out = 'd0; - reg [DW1:0] data_out = 'd0; - - // internal signals - - wire type_s; - wire signext_s; - wire [ DW:0] data_s; - wire [DW1:0] sign_s; - wire [DW1:0] data_out_s; - - // if offset-binary convert to 2's complement first - - assign type_s = dfmt_enable & dfmt_type; - assign signext_s = dfmt_enable & dfmt_se; - - assign data_s = (type_s == 1'b1) ? {~data[DW], data[(DW-1):0]} : data; - assign sign_s = (signext_s == 1'b1) ? {{DW1{data_s[DW]}}} : 0; - - generate - if (DW == DW1) begin - assign data_out_s = data_s; - end else begin - assign data_out_s = {sign_s[DW1:(DW+1)], data_s}; - end - endgenerate - - always @(posedge clk) begin - valid_out <= valid; - data_out <= valid ? data_out_s[DW1:0] : data_out; - end - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad7175/axi_ad7175.v b/library/axi_ad7175/axi_ad7175.v deleted file mode 100644 index 10a9f9d94..000000000 --- a/library/axi_ad7175/axi_ad7175.v +++ /dev/null @@ -1,426 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad7175 ( - - // adc interface (clk, data, over-range) - - adc_sdo_i, - adc_sdi_o, - adc_cs_o, - adc_sclk_o, - adc_clk_i, - led_clk_o, - - // dma interface - - adc_clk, - adc_enable_0, - adc_data_0, - adc_enable_1, - adc_data_1, - adc_enable_2, - adc_data_2, - adc_enable_3, - adc_data_3, - adc_valid_o, - adc_dovf, - adc_dunf, - - // axi interface - - s_axi_aclk, - s_axi_aresetn, - s_axi_awvalid, - s_axi_awaddr, - s_axi_awready, - s_axi_wvalid, - s_axi_wdata, - s_axi_wstrb, - s_axi_wready, - s_axi_bvalid, - s_axi_bresp, - s_axi_bready, - s_axi_arvalid, - s_axi_araddr, - s_axi_arready, - s_axi_rvalid, - s_axi_rresp, - s_axi_rdata, - s_axi_rready); - - // parameters - - parameter PCORE_ID = 0; - parameter PCORE_DEVICE_TYPE = 0; - parameter PCORE_ADC_DP_DISABLE = 0; - parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; - - // adc interface (clk, data, over-range) - - input adc_sdo_i; - output adc_sdi_o; - output adc_cs_o; - output adc_sclk_o; - input adc_clk_i; - output led_clk_o; - - // dma interface - - output adc_clk; - output adc_enable_0; - output [31:0] adc_data_0; - output adc_enable_1; - output [31:0] adc_data_1; - output adc_enable_2; - output [31:0] adc_data_2; - output adc_enable_3; - output [31:0] adc_data_3; - output adc_valid_o; - input adc_dovf; - input adc_dunf; - - - // axi interface - - input s_axi_aclk; - input s_axi_aresetn; - input s_axi_awvalid; - input [31:0] s_axi_awaddr; - output s_axi_awready; - input s_axi_wvalid; - input [31:0] s_axi_wdata; - input [ 3:0] s_axi_wstrb; - output s_axi_wready; - output s_axi_bvalid; - output [ 1:0] s_axi_bresp; - input s_axi_bready; - input s_axi_arvalid; - input [31:0] s_axi_araddr; - output s_axi_arready; - output s_axi_rvalid; - output [ 1:0] s_axi_rresp; - output [31:0] s_axi_rdata; - input s_axi_rready; - - // internal registers - - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; - wire adc_valid_s; - reg adc_valid_d1; - - // internal clocks & resets - - wire adc_rst; - wire up_rstn; - wire up_clk; - wire [13:0] up_waddr_s; - wire [13:0] up_raddr_s; - - // internal signals - - wire adc_status_s; - wire up_sel_s; - wire up_wr_s; - wire [13:0] up_addr_s; - wire [31:0] up_wdata_s; - wire [31:0] up_rdata_s[0:4]; - wire up_rack_s[0:4]; - wire up_wack_s[0:4]; - - wire [31:0] adc_data_s; - wire [ 1:0] adc_reg_rw_s; - wire [31:0] adc_reg_address_s; - wire [31:0] adc_reg_data_w_s; - wire [31:0] adc_rx_data_s; - wire adc_rx_data_rdy_s; - wire adc_tx_data_rdy_s; - wire [31:0] adc_gpio_out; - - wire clk_div_update_rdy_s; - wire [31:0] phase_data_s; - - // signal name changes - assign adc_clk = s_axi_aclk; - assign up_clk = s_axi_aclk; - assign up_rstn = s_axi_aresetn; - assign adc_valid_o = adc_valid_s & ~adc_valid_d1; - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; - end else begin - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4]; - adc_valid_d1 <= adc_valid_s; - end - end - - // channel - - axi_ad7175_channel #( - .CHID(0), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) - i_channel_0 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data ({8'b0, adc_data_s[23:0]}), - .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)), - .adc_data_out (adc_data_0), - .adc_valid (), - .adc_enable (adc_enable_0), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[0]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[0]), - .up_rack (up_rack_s[0])); - -// channel - - axi_ad7175_channel #( - .CHID(1), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) - i_channel_1 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data (phase_data_s), - .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b0)), - .adc_data_out (adc_data_1), - .adc_valid (), - .adc_enable (adc_enable_1), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[1]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[1]), - .up_rack (up_rack_s[1])); - - // channel - - axi_ad7175_channel #( - .CHID(3), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) - i_channel_2 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data ({8'b0, adc_data_s[23:0]}), - .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)), - .adc_data_out (adc_data_2), - .adc_valid (), - .adc_enable (adc_enable_2), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[2]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[2]), - .up_rack (up_rack_s[2])); - - axi_ad7175_channel #( - .CHID(4), - .DP_DISABLE (PCORE_ADC_DP_DISABLE)) - i_channel_3 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data (phase_data_s), - .adc_valid_in(data_rd_ready_s && (adc_data_s[25:24] == 2'b1)), - .adc_data_out (adc_data_3), - .adc_valid (adc_valid_s), - .adc_enable (adc_enable_3), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[3]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[3]), - .up_rack (up_rack_s[3])); - - // clock divider - clk_div clk_div_i ( - .clk_i(s_axi_aclk), - .reset_n_i(up_rstn), - .new_div_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h40)), - .div_i(adc_reg_data_w_s[31:0]), - .new_phase_inc_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] == 8'h41)), - .phase_inc_i(adc_reg_data_w_s[31:0]), - .reg_update_rdy_o(clk_div_update_rdy_s), - .clk_o(led_clk_o), - .phase_o(phase_data_s)); - - // main (device interface) - - ad7175_if ad7175_if_i( - .fpga_clk_i(s_axi_aclk), - .adc_clk_i(adc_clk_i), - .reset_n_i(~adc_rst), - - .start_conversion_i(adc_gpio_out[0]), - .dma_data_o(adc_data_s), - .dma_data_rdy_o(data_rd_ready_s), - - .start_transmission_i(adc_reg_rw_s[1] && (adc_reg_address_s[7:0] < 8'h39)), - .tx_data_i({adc_reg_address_s[7:0], adc_reg_data_w_s[23:0]}), - .tx_data_rdy_o(adc_tx_data_rdy_s), - - .start_read_i(adc_reg_rw_s[0] && (adc_reg_address_s[7:0] < 8'h39)), - .rx_data_o(adc_rx_data_s), - .rx_data_rdy_o(adc_rx_data_rdy_s), - - .adc_sdo_i(adc_sdo_i), - .adc_sdi_o(adc_sdi_o), - .adc_cs_o(adc_cs_o), - .adc_sclk_o(adc_sclk_o), - .adc_status_o(adc_status_s)); - - // common processor control - - up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( - .mmcm_rst (), - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_r1_mode (), - .adc_ddr_edgesel (), - .adc_pin_mode (), - .adc_status (adc_status_s), - .adc_status_ovf (adc_dovf), - .adc_status_unf (adc_dunf), - .adc_clk_ratio (32'd1), - - .adc_reg_address(adc_reg_address_s), - .adc_reg_data_r(adc_rx_data_s), - .adc_reg_data_w(adc_reg_data_w_s), - .adc_reg_rw(adc_reg_rw_s), - .adc_reg_done(adc_tx_data_rdy_s | adc_rx_data_rdy_s | clk_div_update_rdy_s), - - .up_status_pn_err (1'b0), - .up_status_pn_oos (1'b0), - .up_status_or (1'b0), - .delay_clk (), - .delay_rst (), - .delay_sel (), - .delay_rwn (), - .delay_addr (), - .delay_wdata (), - .delay_rdata (), - .delay_ack_t (), - .delay_locked (), - .drp_clk (1'd0), - .drp_rst (), - .drp_sel (), - .drp_wr (), - .drp_addr (), - .drp_wdata (), - .drp_rdata (16'd0), - .drp_ready (1'd0), - .drp_locked (1'd1), - .up_usr_chanmax (), - .adc_usr_chanmax (8'd0), - .up_adc_gpio_in (), - .up_adc_gpio_out (adc_gpio_out), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[4]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[4]), - .up_rack (up_rack_s[4])); - - // up bus interface - - up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata), - .up_rack (up_rack)); - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/axi_ad7175/axi_ad7175_channel.v b/library/axi_ad7175/axi_ad7175_channel.v deleted file mode 100644 index e813c6099..000000000 --- a/library/axi_ad7175/axi_ad7175_channel.v +++ /dev/null @@ -1,174 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// ADC channel- - -`timescale 1ns/100ps - -module axi_ad7175_channel ( - - // adc interface - adc_clk, - adc_rst, - adc_data, - adc_valid_in, - - // channel interface - adc_data_out, - adc_valid, - adc_enable, - - - // processor interface - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters - - parameter CHID = 0; - parameter DP_DISABLE = 0; - - // adc interface - - input adc_clk; - input adc_rst; - input [31:0] adc_data; - input adc_valid_in; - // channel interface - - output [31:0] adc_data_out; - output adc_valid; - output adc_enable; - - // processor interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - - // internal signals - - wire adc_dfmt_se_s; - wire adc_dfmt_type_s; - wire adc_dfmt_enable_s; - - generate - if (DP_DISABLE == 1) begin - assign adc_valid = adc_valid_in; - assign adc_data_out = {8'b0, adc_data}; - end else begin - ad_datafmt #( - .DATA_WIDTH(32), - .DATA_WIDTH_OUT(32)) - i_ad_datafmt ( - .clk (adc_clk), - .valid (adc_valid_in), - .data (adc_data), - .valid_out (adc_valid), - .data_out (adc_data_out), - .dfmt_enable (adc_dfmt_enable_s), - .dfmt_type (adc_dfmt_type_s), - .dfmt_se (adc_dfmt_se_s)); - end - endgenerate - - up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_enable (adc_enable), - .adc_iqcor_enb (), - .adc_dcfilt_enb (), - .adc_dfmt_se (adc_dfmt_se_s), - .adc_dfmt_type (adc_dfmt_type_s), - .adc_dfmt_enable (adc_dfmt_enable_s), - .adc_dcfilt_offset (), - .adc_dcfilt_coeff (), - .adc_iqcor_coeff_1 (), - .adc_iqcor_coeff_2 (), - .adc_pnseq_sel (), - .adc_data_sel (), - .adc_pn_err (), - .adc_pn_oos (), - .adc_or (), - .up_adc_pn_err (), - .up_adc_pn_oos (), - .up_adc_or (), - .up_usr_datatype_be (), - .up_usr_datatype_signed (), - .up_usr_datatype_shift (), - .up_usr_datatype_total_bits (), - .up_usr_datatype_bits (), - .up_usr_decimation_m (), - .up_usr_decimation_n (), - .adc_usr_datatype_be (1'b0), - .adc_usr_datatype_signed (1'b1), - .adc_usr_datatype_shift (8'd0), - .adc_usr_datatype_total_bits (8'd32), - .adc_usr_datatype_bits (8'd32), - .adc_usr_decimation_m (16'd1), - .adc_usr_decimation_n (16'd1), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata), - .up_rack (up_rack)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad7175/axi_ad7175_ip.tcl b/library/axi_ad7175/axi_ad7175_ip.tcl deleted file mode 100644 index 211a2747e..000000000 --- a/library/axi_ad7175/axi_ad7175_ip.tcl +++ /dev/null @@ -1,27 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create axi_ad7175 -adi_ip_files axi_ad7175 [list \ - "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/common/up_axi.v" \ - "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ - "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ - "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ - "$ad_hdl_dir/library/common/up_xfer_status.v" \ - "$ad_hdl_dir/library/common/up_clock_mon.v" \ - "$ad_hdl_dir/library/common/up_adc_channel.v" \ - "up_adc_common.v" \ - "ad_datafmt.v" \ - "ad7175_if.v" \ - "axi_ad7175.v" \ - "axi_ad7175_channel.v" \ - "clk_div.v" ] - -adi_ip_properties axi_ad7175 - -ipx::save_core [ipx::current_core] - - diff --git a/library/axi_ad7175/clk_div.v b/library/axi_ad7175/clk_div.v deleted file mode 100644 index 80ce82b01..000000000 --- a/library/axi_ad7175/clk_div.v +++ /dev/null @@ -1,125 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -//------------------------------------------------------------------------------ -//----------- Module Declaration ----------------------------------------------- -//------------------------------------------------------------------------------ -module clk_div - ( - // Clock and Reset signals - input clk_i, - input reset_n_i, - - // Clock divider - input new_div_i, - input [31:0] div_i, - input new_phase_inc_i, - input [31:0] phase_inc_i, - - // Divided clock output - output reg reg_update_rdy_o, - output clk_o, - output [31:0] phase_o - ); - -//------------------------------------------------------------------------------ -//----------- Registers Declarations ------------------------------------------- -//------------------------------------------------------------------------------ -reg [31:0] div; -reg [31:0] div_cnt; -reg [31:0] phase; -reg [31:0] phase_inc; -reg clk_div; - -//------------------------------------------------------------------------------ -//----------- Assign/Always Blocks --------------------------------------------- -//------------------------------------------------------------------------------ -assign clk_o = clk_div; -assign phase_o = phase; - -// Register update logic -always @(posedge clk_i) -begin - if(reset_n_i == 1'b0) - begin - div <= 'd0; - phase_inc <= 'd0; - reg_update_rdy_o <= 1'b0; - end - else - begin - if(new_div_i == 1'b1) - begin - div <= div_i; - end - if(new_phase_inc_i == 1'b1) - begin - phase_inc <= phase_inc_i; - end - reg_update_rdy_o <= new_div_i | new_phase_inc_i; - end -end - -// Clock division logic -always @(posedge clk_i) -begin - if(reset_n_i == 1'b0) - begin - clk_div <= 'd1; - phase <= 'd0; - end - else - begin - if(div_cnt < div) - begin - div_cnt <= div_cnt + 'd1; - end - else - begin - div_cnt <= 'd1; - //clk_div <= ~clk_div; - end - phase <= phase + phase_inc; - clk_div <= phase[31]; - end -end - -endmodule diff --git a/library/axi_ad7175/up_adc_common.v b/library/axi_ad7175/up_adc_common.v deleted file mode 100644 index 3c8025396..000000000 --- a/library/axi_ad7175/up_adc_common.v +++ /dev/null @@ -1,518 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module up_adc_common ( - - // clock reset - - mmcm_rst, - - // adc interface - - adc_clk, - adc_rst, - adc_r1_mode, - adc_ddr_edgesel, - adc_pin_mode, - adc_status, - adc_sync_status, - adc_status_ovf, - adc_status_unf, - adc_clk_ratio, - adc_start_code, - adc_sync, - adc_reg_address, - adc_reg_data_r, - adc_reg_data_w, - adc_reg_rw, - adc_reg_done, - - // channel interface - - up_status_pn_err, - up_status_pn_oos, - up_status_or, - - // delay interface - - delay_clk, - delay_rst, - delay_sel, - delay_rwn, - delay_addr, - delay_wdata, - delay_rdata, - delay_ack_t, - delay_locked, - - // drp interface - - drp_clk, - drp_rst, - drp_sel, - drp_wr, - drp_addr, - drp_wdata, - drp_rdata, - drp_ready, - drp_locked, - - // user channel control - - up_usr_chanmax, - adc_usr_chanmax, - up_adc_gpio_in, - up_adc_gpio_out, - - // bus interface - - up_rstn, - up_clk, - up_wreq, - up_waddr, - up_wdata, - up_wack, - up_rreq, - up_raddr, - up_rdata, - up_rack); - - // parameters - - localparam PCORE_VERSION = 32'h00080062; - parameter PCORE_ID = 0; - - // clock reset - - output mmcm_rst; - - // adc interface - - input adc_clk; - output adc_rst; - output adc_r1_mode; - output adc_ddr_edgesel; - output adc_pin_mode; - input adc_status; - input adc_sync_status; - input adc_status_ovf; - input adc_status_unf; - input [31:0] adc_clk_ratio; - output [31:0] adc_start_code; - output adc_sync; - output [31:0] adc_reg_address; - input [31:0] adc_reg_data_r; - output [31:0] adc_reg_data_w; - output [ 1:0] adc_reg_rw; - input adc_reg_done; - - // channel interface - - input up_status_pn_err; - input up_status_pn_oos; - input up_status_or; - - // delay interface - - input delay_clk; - output delay_rst; - output delay_sel; - output delay_rwn; - output [ 7:0] delay_addr; - output [ 4:0] delay_wdata; - input [ 4:0] delay_rdata; - input delay_ack_t; - input delay_locked; - - // drp interface - - input drp_clk; - output drp_rst; - output drp_sel; - output drp_wr; - output [11:0] drp_addr; - output [15:0] drp_wdata; - input [15:0] drp_rdata; - input drp_ready; - input drp_locked; - - // user channel control - - output [ 7:0] up_usr_chanmax; - input [ 7:0] adc_usr_chanmax; - input [31:0] up_adc_gpio_in; - output [31:0] up_adc_gpio_out; - - // bus interface - - input up_rstn; - input up_clk; - input up_wreq; - input [13:0] up_waddr; - input [31:0] up_wdata; - output up_wack; - input up_rreq; - input [13:0] up_raddr; - output [31:0] up_rdata; - output up_rack; - - // internal registers - - reg up_wack = 'd0; - reg [31:0] up_scratch = 'd0; - reg up_mmcm_resetn = 'd0; - reg up_resetn = 'd0; - reg up_adc_r1_mode = 'd0; - reg up_adc_ddr_edgesel = 'd0; - reg up_adc_pin_mode = 'd0; - reg up_delay_sel = 'd0; - reg up_delay_rwn = 'd0; - reg [ 7:0] up_delay_addr = 'd0; - reg [ 4:0] up_delay_wdata = 'd0; - reg up_drp_sel_t = 'd0; - reg up_drp_rwn = 'd0; - reg [11:0] up_drp_addr = 'd0; - reg [15:0] up_drp_wdata = 'd0; - reg up_status_ovf = 'd0; - reg up_status_unf = 'd0; - reg [ 7:0] up_usr_chanmax = 'd0; - reg [31:0] up_adc_gpio_out = 'd0; - reg [31:0] up_adc_start_code = 'd0; - reg up_adc_sync = 'd0; - reg up_rack = 'd0; - reg [31:0] up_rdata = 'd0; - reg [31:0] up_adc_reg_address = 'd0; - reg [31:0] up_adc_reg_data = 'd0; - reg up_adc_reg_write = 'd0; - reg up_adc_reg_read = 'd0; - - // internal signals - - wire up_wreq_s; - wire up_rreq_s; - wire up_preset_s; - wire up_mmcm_preset_s; - wire up_status_s; - wire up_sync_status_s; - wire up_status_ovf_s; - wire up_status_unf_s; - wire up_cntrl_xfer_done; - wire [31:0] up_adc_clk_count_s; - wire [ 4:0] up_delay_rdata_s; - wire up_delay_status_s; - wire up_delay_locked_s; - wire [15:0] up_drp_rdata_s; - wire up_drp_status_s; - wire up_drp_locked_s; - wire [31:0] up_adc_reg_data_s; - wire up_adc_reg_done_s; - - // decode block select - - assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; - assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; - assign up_preset_s = ~up_resetn; - assign up_mmcm_preset_s = ~up_mmcm_resetn; - - // processor write interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_wack <= 'd0; - up_scratch <= 'd0; - up_mmcm_resetn <= 'd0; - up_resetn <= 'd0; - up_adc_r1_mode <= 'd0; - up_adc_ddr_edgesel <= 'd0; - up_adc_pin_mode <= 'd0; - up_delay_sel <= 'd0; - up_delay_rwn <= 'd0; - up_delay_addr <= 'd0; - up_delay_wdata <= 'd0; - up_drp_sel_t <= 'd0; - up_drp_rwn <= 'd0; - up_drp_addr <= 'd0; - up_drp_wdata <= 'd0; - up_status_ovf <= 'd0; - up_status_unf <= 'd0; - up_usr_chanmax <= 'd0; - up_adc_gpio_out <= 'd0; - up_adc_start_code <= 'd0; - up_adc_reg_address <= 'd0; - up_adc_reg_data <= 'd0; - up_adc_reg_read <= 'd0; - up_adc_reg_write <= 'd0; - end else begin - up_wack <= up_wreq_s; - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin - up_scratch <= up_wdata; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin - up_mmcm_resetn <= up_wdata[1]; - up_resetn <= up_wdata[0]; - end - if (up_adc_sync == 1'b1) begin - if (up_cntrl_xfer_done == 1'b1) begin - up_adc_sync <= 1'b0; - end - end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin - up_adc_sync <= up_wdata[3]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin - up_adc_r1_mode <= up_wdata[2]; - up_adc_ddr_edgesel <= up_wdata[1]; - up_adc_pin_mode <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin - up_adc_reg_address <= up_wdata; - end - - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin - up_adc_reg_data <= up_wdata; - end - else if((up_adc_reg_done_s == 1'b1) && (up_adc_reg_read == 1'b1)) - begin - up_adc_reg_data <= up_adc_reg_data_s; - end - - if (up_adc_reg_read == 1'b1) begin - if (up_adc_reg_done_s == 1'b1) begin - up_adc_reg_read <= 1'b0; - end - end else if (up_adc_reg_write == 1'b1) begin - if (up_adc_reg_done_s == 1'b1) begin - up_adc_reg_write <= 1'b0; - end - end - else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin - up_adc_reg_write <= up_wdata[1]; - up_adc_reg_read <= up_wdata[0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h18)) begin - up_delay_sel <= up_wdata[17]; - up_delay_rwn <= up_wdata[16]; - up_delay_addr <= up_wdata[15:8]; - up_delay_wdata <= up_wdata[4:0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin - up_drp_sel_t <= ~up_drp_sel_t; - up_drp_rwn <= up_wdata[28]; - up_drp_addr <= up_wdata[27:16]; - up_drp_wdata <= up_wdata[15:0]; - end - if (up_status_ovf_s == 1'b1) begin - up_status_ovf <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin - up_status_ovf <= up_status_ovf & ~up_wdata[2]; - end - if (up_status_unf_s == 1'b1) begin - up_status_unf <= 1'b1; - end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin - up_status_unf <= up_status_unf & ~up_wdata[1]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin - up_usr_chanmax <= up_wdata[7:0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin - up_adc_start_code <= up_wdata[31:0]; - end - if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin - up_adc_gpio_out <= up_wdata; - end - end - end - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rack <= 'd0; - up_rdata <= 'd0; - end else begin - up_rack <= up_rreq_s; - if (up_rreq_s == 1'b1) begin - case (up_raddr[7:0]) - 8'h00: up_rdata <= PCORE_VERSION; - 8'h01: up_rdata <= PCORE_ID; - 8'h02: up_rdata <= up_scratch; - 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; - 8'h11: up_rdata <= {28'd0, up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; - 8'h12: up_rdata <= up_adc_reg_address; - 8'h13: up_rdata <= up_adc_reg_data; - 8'h14: up_rdata <= {30'd0, up_adc_reg_write, up_adc_reg_read}; - 8'h15: up_rdata <= up_adc_clk_count_s; - 8'h16: up_rdata <= adc_clk_ratio; - 8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; - 8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata}; - 8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s}; - 8'h1a: up_rdata <= {31'd0, up_sync_status_s}; - 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; - 8'h1d: up_rdata <= {14'd0, up_drp_locked_s, up_drp_status_s, up_drp_rdata_s}; - 8'h22: up_rdata <= {29'd0, up_status_ovf, up_status_unf, 1'b0}; - 8'h23: up_rdata <= 32'd8; - 8'h28: up_rdata <= {24'd0, adc_usr_chanmax}; - 8'h29: up_rdata <= up_adc_start_code; - 8'h2e: up_rdata <= up_adc_gpio_in; - 8'h2f: up_rdata <= up_adc_gpio_out; - default: up_rdata <= 0; - endcase - end else begin - up_rdata <= 32'd0; - end - end - end - - // resets - - ad_rst i_mmcm_rst_reg (.preset(up_mmcm_preset_s), .clk(drp_clk), .rst(mmcm_rst)); - ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst)); - ad_rst i_delay_rst_reg (.preset(up_preset_s), .clk(delay_clk), .rst(delay_rst)); - ad_rst i_drp_rst_reg (.preset(up_preset_s), .clk(drp_clk), .rst(drp_rst)); - - // adc control & status - - up_xfer_cntrl #(.DATA_WIDTH(70)) i_adc_xfer_cntrl ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_cntrl ({ up_adc_reg_address, - up_adc_reg_data, - up_adc_reg_write, - up_adc_reg_read, - up_adc_sync, - up_adc_r1_mode, - up_adc_ddr_edgesel, - up_adc_pin_mode}), - .up_xfer_done (up_cntrl_xfer_done), - .d_rst (adc_rst), - .d_clk (adc_clk), - .d_data_cntrl ({ adc_reg_address, - adc_reg_data_w, - adc_reg_rw[1], - adc_reg_rw[0], - adc_sync, - adc_r1_mode, - adc_ddr_edgesel, - adc_pin_mode})); - - up_xfer_status #(.DATA_WIDTH(37)) i_adc_xfer_status ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_status ({up_adc_reg_data_s, - up_adc_reg_done_s, - up_sync_status_s, - up_status_s, - up_status_ovf_s, - up_status_unf_s}), - .d_rst (adc_rst), - .d_clk (adc_clk), - .d_data_status ({ adc_reg_data_r, - adc_reg_done, - adc_sync_status, - adc_status, - adc_status_ovf, - adc_status_unf})); - - up_xfer_cntrl #(.DATA_WIDTH(32)) i_adc_xfer_start_code ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_data_cntrl (up_adc_start_code), - .up_xfer_done (), - .d_rst (adc_rst), - .d_clk (adc_clk), - .d_data_cntrl (adc_start_code)); - - // adc clock monitor - - up_clock_mon i_adc_clock_mon ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_d_count (up_adc_clk_count_s), - .d_rst (adc_rst), - .d_clk (adc_clk)); - - // delay control & status - - up_delay_cntrl i_delay_cntrl ( - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_sel (delay_sel), - .delay_rwn (delay_rwn), - .delay_addr (delay_addr), - .delay_wdata (delay_wdata), - .delay_rdata (delay_rdata), - .delay_ack_t (delay_ack_t), - .delay_locked (delay_locked), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_delay_sel (up_delay_sel), - .up_delay_rwn (up_delay_rwn), - .up_delay_addr (up_delay_addr), - .up_delay_wdata (up_delay_wdata), - .up_delay_rdata (up_delay_rdata_s), - .up_delay_status (up_delay_status_s), - .up_delay_locked (up_delay_locked_s)); - - // drp control & status - - up_drp_cntrl i_drp_cntrl ( - .drp_clk (drp_clk), - .drp_rst (drp_rst), - .drp_sel (drp_sel), - .drp_wr (drp_wr), - .drp_addr (drp_addr), - .drp_wdata (drp_wdata), - .drp_rdata (drp_rdata), - .drp_ready (drp_ready), - .drp_locked (drp_locked), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_drp_sel_t (up_drp_sel_t), - .up_drp_rwn (up_drp_rwn), - .up_drp_addr (up_drp_addr), - .up_drp_wdata (up_drp_wdata), - .up_drp_rdata (up_drp_rdata_s), - .up_drp_status (up_drp_status_s), - .up_drp_locked (up_drp_locked_s)); - -endmodule - -// *************************************************************************** -// ***************************************************************************