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Remove old util_cpack and util_upack core 

All projects have been updated to use the new pack/unpack infrastructure.
The old util_cpack and util_upack cores are now unused an can be removed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-10-04 13:10:48 +02:00 committed by Adrian Costina
parent bf50916a3f
commit a0309e3e3a
13 changed files with 0 additions and 6901 deletions
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4
library/Makefile
View File

@ -91,7 +91,6 @@ clean:
$(MAKE) -C util_cdc clean
$(MAKE) -C util_cic clean
$(MAKE) -C util_clkdiv clean
$(MAKE) -C util_cpack clean
$(MAKE) -C util_dacfifo clean
$(MAKE) -C util_delay clean
$(MAKE) -C util_extract clean
@ -106,7 +105,6 @@ clean:
$(MAKE) -C util_rfifo clean
$(MAKE) -C util_sigma_delta_spi clean
$(MAKE) -C util_tdd_sync clean
$(MAKE) -C util_upack clean
$(MAKE) -C util_var_fifo clean
$(MAKE) -C util_wfifo clean
$(MAKE) -C xilinx/axi_adcfifo clean
@ -201,7 +199,6 @@ lib:
$(MAKE) -C util_cdc
$(MAKE) -C util_cic
$(MAKE) -C util_clkdiv
$(MAKE) -C util_cpack
$(MAKE) -C util_dacfifo
$(MAKE) -C util_delay
$(MAKE) -C util_extract
@ -216,7 +213,6 @@ lib:
$(MAKE) -C util_rfifo
$(MAKE) -C util_sigma_delta_spi
$(MAKE) -C util_tdd_sync
$(MAKE) -C util_upack
$(MAKE) -C util_var_fifo
$(MAKE) -C util_wfifo
$(MAKE) -C xilinx/axi_adcfifo

16
library/util_cpack/Makefile
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@ -1,16 +0,0 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_cpack
GENERIC_DEPS += util_cpack.v
GENERIC_DEPS += util_cpack_dsf.v
GENERIC_DEPS += util_cpack_mux.v
XILINX_DEPS += util_cpack_ip.tcl
ALTERA_DEPS += util_cpack_hw.tcl
include ../scripts/library.mk

274
library/util_cpack/util_cpack.v
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@ -1,274 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_cpack #(
parameter CHANNEL_DATA_WIDTH = 32,
parameter NUM_OF_CHANNELS = 8) (
// adc interface
input adc_rst,
input adc_clk,
input adc_enable_0,
input adc_valid_0,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_0,
input adc_enable_1,
input adc_valid_1,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_1,
input adc_enable_2,
input adc_valid_2,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_2,
input adc_enable_3,
input adc_valid_3,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_3,
input adc_enable_4,
input adc_valid_4,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_4,
input adc_enable_5,
input adc_valid_5,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_5,
input adc_enable_6,
input adc_valid_6,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_6,
input adc_enable_7,
input adc_valid_7,
input [(CHANNEL_DATA_WIDTH-1):0] adc_data_7,
// fifo interface
output reg adc_valid,
output reg adc_sync,
output reg [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] adc_data);
localparam SAMPLES_PCHANNEL = CHANNEL_DATA_WIDTH/16;
localparam NUM_OF_CHANNELS_M = 8;
localparam BUS_DATA_WIDTH = NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH;
localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS;
// internal registers
reg adc_valid_d = 'd0;
reg [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_d = 'd0;
reg adc_mux_valid = 'd0;
reg [(NUM_OF_CHANNELS_M-1):0] adc_mux_enable = 'd0;
reg [((SAMPLES_PCHANNEL*16*79)-1):0] adc_mux_data = 'd0;
// internal signals
wire [(NUM_OF_CHANNELS_M-1):0] adc_enable_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_valid_s;
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_s;
wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] adc_data_intlv_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_valid_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_0_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_1_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_2_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_3_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_4_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_5_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_6_s;
wire [(SAMPLES_PCHANNEL-1):0] adc_mux_enable_7_s;
wire [((SAMPLES_PCHANNEL*16*1)-1):0] adc_mux_data_0_s;
wire [((SAMPLES_PCHANNEL*16*2)-1):0] adc_mux_data_1_s;
wire [((SAMPLES_PCHANNEL*16*3)-1):0] adc_mux_data_2_s;
wire [((SAMPLES_PCHANNEL*16*4)-1):0] adc_mux_data_3_s;
wire [((SAMPLES_PCHANNEL*16*5)-1):0] adc_mux_data_4_s;
wire [((SAMPLES_PCHANNEL*16*6)-1):0] adc_mux_data_5_s;
wire [((SAMPLES_PCHANNEL*16*7)-1):0] adc_mux_data_6_s;
wire [((SAMPLES_PCHANNEL*16*8)-1):0] adc_mux_data_7_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_valid_s;
wire [(NUM_OF_CHANNELS_M-1):0] adc_dsf_sync_s;
wire [(BUS_DATA_WIDTH-1):0] adc_dsf_data_s[(NUM_OF_CHANNELS_M-1):0];
// loop variables
genvar n;
// making things a bit easier
assign adc_enable_s = { adc_enable_7, adc_enable_6, adc_enable_5, adc_enable_4,
adc_enable_3, adc_enable_2, adc_enable_1, adc_enable_0};
assign adc_valid_s = { adc_valid_7, adc_valid_6, adc_valid_5, adc_valid_4,
adc_valid_3, adc_valid_2, adc_valid_1, adc_valid_0};
assign adc_data_s = { adc_data_7, adc_data_6, adc_data_5, adc_data_4,
adc_data_3, adc_data_2, adc_data_1, adc_data_0};
// adc first channel must be always on (doesn't have to be enabled)
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_valid_d <= 'd0;
end else begin
adc_valid_d <= adc_valid_0;
end
end
// mw requires unused to be zero
generate
for (n = 0; n < NUM_OF_CHANNELS_M; n = n + 1) begin: g_in
always @(posedge adc_clk) begin
if ((adc_rst == 1'b1) && (adc_enable_s[n] == 1'b0)) begin
adc_data_d[((CHANNEL_DATA_WIDTH*(n+1))-1):(CHANNEL_DATA_WIDTH*n)] <= 'd0;
end else if (adc_valid_s[n] == 1'b1) begin
adc_data_d[((CHANNEL_DATA_WIDTH*(n+1))-1):(CHANNEL_DATA_WIDTH*n)] <=
adc_data_s[((CHANNEL_DATA_WIDTH*(n+1))-1):(CHANNEL_DATA_WIDTH*n)];
end
end
end
endgenerate
// interleave data
generate
for (n = 0; n < SAMPLES_PCHANNEL; n = n + 1) begin: g_intlv
assign adc_data_intlv_s[((16*NUM_OF_CHANNELS_M*(n+1))-1):(16*NUM_OF_CHANNELS_M*n)] =
{ adc_data_d[(((CHANNEL_DATA_WIDTH*7)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*7)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*6)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*6)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*5)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*5)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*4)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*4)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*3)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*3)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*2)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*2)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*1)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*1)+(16*n))],
adc_data_d[(((CHANNEL_DATA_WIDTH*0)+(16*(n+1)))-1):((CHANNEL_DATA_WIDTH*0)+(16*n))]};
end
endgenerate
// mux
generate
for (n = 0; n < SAMPLES_PCHANNEL; n = n + 1) begin: g_mux
util_cpack_mux i_mux (
.adc_clk (adc_clk),
.adc_valid (adc_valid_d),
.adc_enable (adc_enable_s),
.adc_data (adc_data_intlv_s[((16*NUM_OF_CHANNELS_M*(n+1))-1):(16*NUM_OF_CHANNELS_M*n)]),
.adc_mux_valid (adc_mux_valid_s[n]),
.adc_mux_enable_0 (adc_mux_enable_0_s[n]),
.adc_mux_data_0 (adc_mux_data_0_s[(((n+1)*16*1)-1):(n*16*1)]),
.adc_mux_enable_1 (adc_mux_enable_1_s[n]),
.adc_mux_data_1 (adc_mux_data_1_s[(((n+1)*16*2)-1):(n*16*2)]),
.adc_mux_enable_2 (adc_mux_enable_2_s[n]),
.adc_mux_data_2 (adc_mux_data_2_s[(((n+1)*16*3)-1):(n*16*3)]),
.adc_mux_enable_3 (adc_mux_enable_3_s[n]),
.adc_mux_data_3 (adc_mux_data_3_s[(((n+1)*16*4)-1):(n*16*4)]),
.adc_mux_enable_4 (adc_mux_enable_4_s[n]),
.adc_mux_data_4 (adc_mux_data_4_s[(((n+1)*16*5)-1):(n*16*5)]),
.adc_mux_enable_5 (adc_mux_enable_5_s[n]),
.adc_mux_data_5 (adc_mux_data_5_s[(((n+1)*16*6)-1):(n*16*6)]),
.adc_mux_enable_6 (adc_mux_enable_6_s[n]),
.adc_mux_data_6 (adc_mux_data_6_s[(((n+1)*16*7)-1):(n*16*7)]),
.adc_mux_enable_7 (adc_mux_enable_7_s[n]),
.adc_mux_data_7 (adc_mux_data_7_s[(((n+1)*16*8)-1):(n*16*8)]));
end
endgenerate
// concat
always @(posedge adc_clk) begin
adc_mux_valid <= & adc_mux_valid_s;
adc_mux_enable[0] <= & adc_mux_enable_0_s;
adc_mux_enable[1] <= & adc_mux_enable_1_s;
adc_mux_enable[2] <= & adc_mux_enable_2_s;
adc_mux_enable[3] <= & adc_mux_enable_3_s;
adc_mux_enable[4] <= & adc_mux_enable_4_s;
adc_mux_enable[5] <= & adc_mux_enable_5_s;
adc_mux_enable[6] <= & adc_mux_enable_6_s;
adc_mux_enable[7] <= & adc_mux_enable_7_s;
adc_mux_data[((SAMPLES_PCHANNEL*16* 9)-1):(SAMPLES_PCHANNEL*16* 1)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*19)-1):(SAMPLES_PCHANNEL*16*12)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*29)-1):(SAMPLES_PCHANNEL*16*23)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*39)-1):(SAMPLES_PCHANNEL*16*34)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*49)-1):(SAMPLES_PCHANNEL*16*45)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*59)-1):(SAMPLES_PCHANNEL*16*56)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*69)-1):(SAMPLES_PCHANNEL*16*67)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16*79)-1):(SAMPLES_PCHANNEL*16*78)] <= 'd0;
adc_mux_data[((SAMPLES_PCHANNEL*16* 1)-1):(SAMPLES_PCHANNEL*16* 0)] <= adc_mux_data_0_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*12)-1):(SAMPLES_PCHANNEL*16*10)] <= adc_mux_data_1_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*23)-1):(SAMPLES_PCHANNEL*16*20)] <= adc_mux_data_2_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*34)-1):(SAMPLES_PCHANNEL*16*30)] <= adc_mux_data_3_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*45)-1):(SAMPLES_PCHANNEL*16*40)] <= adc_mux_data_4_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*56)-1):(SAMPLES_PCHANNEL*16*50)] <= adc_mux_data_5_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*67)-1):(SAMPLES_PCHANNEL*16*60)] <= adc_mux_data_6_s;
adc_mux_data[((SAMPLES_PCHANNEL*16*78)-1):(SAMPLES_PCHANNEL*16*70)] <= adc_mux_data_7_s;
end
// store & fwd
generate
for (n = 0; n < NUM_OF_CHANNELS_P; n = n + 1) begin: g_dsf
util_cpack_dsf #(
.NUM_OF_CHANNELS_M (NUM_OF_CHANNELS_M),
.NUM_OF_CHANNELS_P (NUM_OF_CHANNELS_P),
.CHANNEL_DATA_WIDTH (CHANNEL_DATA_WIDTH),
.NUM_OF_CHANNELS_I ((n+1)))
i_dsf (
.adc_clk (adc_clk),
.adc_valid (adc_mux_valid),
.adc_enable (adc_mux_enable[n]),
.adc_data (adc_mux_data[((SAMPLES_PCHANNEL*16*((11*n)+1))-1):(SAMPLES_PCHANNEL*16*10*n)]),
.adc_dsf_valid (adc_dsf_valid_s[n]),
.adc_dsf_sync (adc_dsf_sync_s[n]),
.adc_dsf_data (adc_dsf_data_s[n]));
end
endgenerate
generate
if (NUM_OF_CHANNELS_M > NUM_OF_CHANNELS_P) begin
for (n = NUM_OF_CHANNELS_P; n < NUM_OF_CHANNELS_M; n = n + 1) begin: g_def
assign adc_dsf_valid_s[n] = 'd0;
assign adc_dsf_sync_s[n] = 'd0;
assign adc_dsf_data_s[n] = 'd0;
end
end
endgenerate
always @(posedge adc_clk) begin
adc_valid <= | adc_dsf_valid_s;
adc_sync <= | adc_dsf_sync_s;
adc_data <= adc_dsf_data_s[7] | adc_dsf_data_s[6] |
adc_dsf_data_s[5] | adc_dsf_data_s[4] |
adc_dsf_data_s[3] | adc_dsf_data_s[2] |
adc_dsf_data_s[1] | adc_dsf_data_s[0];
end
endmodule
// ***************************************************************************
// ***************************************************************************

173
library/util_cpack/util_cpack_dsf.v
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@ -1,173 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_cpack_dsf #(
parameter CHANNEL_DATA_WIDTH = 32,
parameter NUM_OF_CHANNELS_I = 4,
parameter NUM_OF_CHANNELS_M = 8,
parameter NUM_OF_CHANNELS_P = 4) (
// adc interface
input adc_clk,
input adc_valid,
input adc_enable,
input [(CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_I-1):0] adc_data,
// dma interface
output reg adc_dsf_valid,
output reg adc_dsf_sync,
output reg [(CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P-1):0] adc_dsf_data);
localparam CH_DCNT = NUM_OF_CHANNELS_P - NUM_OF_CHANNELS_I;
localparam I_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_I;
localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P;
localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M;
// internal registers
reg [ 2:0] adc_samples_int = 'd0;
reg [(M_WIDTH-1):0] adc_data_int = 'd0;
// internal signals
wire [(M_WIDTH-1):0] adc_data_s;
// bypass
generate
if (NUM_OF_CHANNELS_I == NUM_OF_CHANNELS_P) begin
assign adc_data_s = 'd0;
always @(posedge adc_clk) begin
adc_samples_int <= 'd0;
adc_data_int <= 'd0;
if (adc_enable == 1'b1) begin
adc_dsf_valid <= adc_valid;
adc_dsf_sync <= 1'b1;
adc_dsf_data <= adc_data;
end else begin
adc_dsf_valid <= 'b0;
adc_dsf_sync <= 'b0;
adc_dsf_data <= 'd0;
end
end
end
endgenerate
// data store & forward
generate
if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_I) begin
reg adc_dsf_valid_int = 'd0;
reg adc_dsf_sync_int = 'd0;
reg [(P_WIDTH-1):0] adc_dsf_data_int = 'd0;
assign adc_data_s[(M_WIDTH-1):I_WIDTH] = 'd0;
assign adc_data_s[(I_WIDTH-1):0] = adc_data;
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
if (adc_samples_int >= CH_DCNT) begin
adc_samples_int <= adc_samples_int - CH_DCNT;
end else begin
adc_samples_int <= adc_samples_int + NUM_OF_CHANNELS_I;
end
adc_data_int <= {adc_data_s[(I_WIDTH-1):0],
adc_data_int[(M_WIDTH-1):I_WIDTH]};
end
end
always @(posedge adc_clk) begin
if (adc_samples_int >= CH_DCNT) begin
adc_dsf_valid_int <= adc_valid;
end else begin
adc_dsf_valid_int <= 1'b0;
end
if (adc_dsf_sync_int == 1'b1) begin
if (adc_dsf_valid_int == 1'b1) begin
adc_dsf_sync_int <= 1'b0;
end
end else begin
if (adc_samples_int == 3'd0) begin
adc_dsf_sync_int <= 1'b1;
end
end
end
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
case (adc_samples_int)
3'b111: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*1)-1):0],
adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*1)]};
3'b110: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*2)-1):0],
adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*2)]};
3'b101: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*3)-1):0],
adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*3)]};
3'b100: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*4)-1):0],
adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*4)]};
3'b011: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*5)-1):0],
adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*5)]};
3'b010: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*6)-1):0],
adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*6)]};
3'b001: adc_dsf_data_int <= {adc_data_s[((CHANNEL_DATA_WIDTH*7)-1):0],
adc_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]};
3'b000: adc_dsf_data_int <= adc_data_s;
default: adc_dsf_data_int <= 'd0;
endcase
end
end
always @(posedge adc_clk) begin
if (adc_enable == 1'b1) begin
adc_dsf_valid <= adc_dsf_valid_int;
adc_dsf_sync <= adc_dsf_sync_int;
adc_dsf_data <= adc_dsf_data_int[(P_WIDTH-1):0];
end else begin
adc_dsf_valid <= 'b0;
adc_dsf_sync <= 'b0;
adc_dsf_data <= 'd0;
end
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

68
library/util_cpack/util_cpack_hw.tcl
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@ -1,68 +0,0 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME util_cpack
set_module_property DESCRIPTION "Channel Pack Utility"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_cpack
set_module_property ELABORATION_CALLBACK p_util_cpack
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL util_cpack
add_fileset_file util_cpack_mux.v VERILOG PATH util_cpack_mux.v
add_fileset_file util_cpack_dsf.v VERILOG PATH util_cpack_dsf.v
add_fileset_file util_cpack.v VERILOG PATH util_cpack.v TOP_LEVEL_FILE
# parameters
add_parameter CHANNEL_DATA_WIDTH INTEGER 0
set_parameter_property CHANNEL_DATA_WIDTH DEFAULT_VALUE 32
set_parameter_property CHANNEL_DATA_WIDTH DISPLAY_NAME CHANNEL_DATA_WIDTH
set_parameter_property CHANNEL_DATA_WIDTH TYPE INTEGER
set_parameter_property CHANNEL_DATA_WIDTH UNITS None
set_parameter_property CHANNEL_DATA_WIDTH HDL_PARAMETER true
add_parameter NUM_OF_CHANNELS INTEGER 0
set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8
set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
set_parameter_property NUM_OF_CHANNELS TYPE INTEGER
set_parameter_property NUM_OF_CHANNELS UNITS None
set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
# defaults
ad_alt_intf clock adc_clk input 1
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_valid output 1 valid
ad_alt_intf signal adc_sync output 1 sync
ad_alt_intf signal adc_data output NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data
for {set n 0} {$n < 8} {incr n} {
add_interface adc_ch_${n} conduit end
add_interface_port adc_ch_${n} adc_enable_${n} enable Input 1
add_interface_port adc_ch_${n} adc_valid_${n} valid Input 1
add_interface_port adc_ch_${n} adc_data_${n} data Input CHANNEL_DATA_WIDTH
set_interface_property adc_ch_${n} associatedClock if_adc_clk
set_interface_property adc_ch_${n} associatedReset none
}
proc p_util_cpack {} {
set num_channels [get_parameter_value NUM_OF_CHANNELS]
for {set n 1} {$n < 8} {incr n} {
if {$n >= $num_channels} {
set_interface_property adc_ch_${n} ENABLED false
}
}
}

36
library/util_cpack/util_cpack_ip.tcl
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_cpack
adi_ip_files util_cpack [list \
"util_cpack_mux.v" \
"util_cpack_dsf.v" \
"util_cpack.v" ]
adi_ip_properties_lite util_cpack
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
[ipx::get_ports *_1* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
[ipx::get_ports *_2* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \
[ipx::get_ports *_3* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \
[ipx::get_ports *_4* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \
[ipx::get_ports *_5* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \
[ipx::get_ports *_6* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
[ipx::get_ports *_7* -of_objects [ipx::current_core]]
ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]

2138
library/util_cpack/util_cpack_mux.v
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16
library/util_upack/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_upack
GENERIC_DEPS += util_upack.v
GENERIC_DEPS += util_upack_dmx.v
GENERIC_DEPS += util_upack_dsf.v
XILINX_DEPS += util_upack_ip.tcl
ALTERA_DEPS += util_upack_hw.tcl
include ../scripts/library.mk

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library/util_upack/util_upack.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_upack #(
parameter CHANNEL_DATA_WIDTH = 32,
parameter NUM_OF_CHANNELS = 8) (
// dac interface
input dac_clk,
input dac_enable_0,
input dac_valid_0,
output dac_valid_out_0,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0,
input dac_enable_1,
input dac_valid_1,
output dac_valid_out_1,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1,
input dac_enable_2,
input dac_valid_2,
output dac_valid_out_2,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2,
input dac_enable_3,
input dac_valid_3,
output dac_valid_out_3,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3,
input dac_enable_4,
input dac_valid_4,
output dac_valid_out_4,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4,
input dac_enable_5,
input dac_valid_5,
output dac_valid_out_5,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5,
input dac_enable_6,
input dac_valid_6,
output dac_valid_out_6,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6,
input dac_enable_7,
input dac_valid_7,
output dac_valid_out_7,
output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7,
// fifo interface
output dac_valid,
output dac_sync,
input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data);
// internal parameters
localparam MAX_CHANNELS = 8;
// internal registers
reg dac_valid_int = 'd0;
reg dac_sync_int = 'd0;
// internal signals
wire dac_valid_s;
wire [ 7:0] dac_enable_s;
wire dac_dsf_valid_m_s;
wire [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data_m_s;
wire [ 7:0] dac_dmx_enable_m_s;
wire [(MAX_CHANNELS-1):0] dac_dsf_req_s;
wire [(MAX_CHANNELS-1):0] dac_dsf_sync_s;
wire [(MAX_CHANNELS-1):0] dac_dsf_valid_s;
wire [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data_s[(MAX_CHANNELS-1):0];
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_valid_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_7_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_6_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_5_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_4_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_3_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_2_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_1_s;
wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_0_s;
// data interleaving
assign dac_valid = dac_valid_int;
assign dac_sync = dac_sync_int;
assign dac_valid_out_0 = dac_dmx_valid_s[0];
assign dac_valid_out_1 = dac_dmx_valid_s[0];
assign dac_valid_out_2 = dac_dmx_valid_s[0];
assign dac_valid_out_3 = dac_dmx_valid_s[0];
assign dac_valid_out_4 = dac_dmx_valid_s[0];
assign dac_valid_out_5 = dac_dmx_valid_s[0];
assign dac_valid_out_6 = dac_dmx_valid_s[0];
assign dac_valid_out_7 = dac_dmx_valid_s[0];
always @(posedge dac_clk) begin
dac_valid_int <= | dac_dsf_req_s;
dac_sync_int <= | dac_dsf_sync_s;
end
assign dac_valid_s = dac_valid_7 | dac_valid_6 | dac_valid_5 | dac_valid_4 |
dac_valid_3 | dac_valid_2 | dac_valid_1 | dac_valid_0;
assign dac_enable_s = {dac_enable_7, dac_enable_6, dac_enable_5, dac_enable_4,
dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0};
assign dac_dsf_valid_m_s = | dac_dsf_valid_s;
assign dac_dsf_data_m_s = dac_dsf_data_s[7] | dac_dsf_data_s[6] |
dac_dsf_data_s[5] | dac_dsf_data_s[4] | dac_dsf_data_s[3] |
dac_dsf_data_s[2] | dac_dsf_data_s[1] | dac_dsf_data_s[0];
assign dac_dmx_enable_m_s[7] = | dac_dmx_enable_7_s;
assign dac_dmx_enable_m_s[6] = | dac_dmx_enable_6_s;
assign dac_dmx_enable_m_s[5] = | dac_dmx_enable_5_s;
assign dac_dmx_enable_m_s[4] = | dac_dmx_enable_4_s;
assign dac_dmx_enable_m_s[3] = | dac_dmx_enable_3_s;
assign dac_dmx_enable_m_s[2] = | dac_dmx_enable_2_s;
assign dac_dmx_enable_m_s[1] = | dac_dmx_enable_1_s;
assign dac_dmx_enable_m_s[0] = | dac_dmx_enable_0_s;
// instantiations
genvar n;
generate
// defaults
for (n = NUM_OF_CHANNELS; n < MAX_CHANNELS; n = n + 1) begin: g_defaults
assign dac_dsf_req_s[n] = 'd0;
assign dac_dsf_sync_s[n] = 'd0;
assign dac_dsf_valid_s[n] = 'd0;
assign dac_dsf_data_s[n] = 'd0;
end
// dsf
for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_dsf
util_upack_dsf #(
.CHANNEL_DATA_WIDTH (CHANNEL_DATA_WIDTH),
.NUM_OF_CHANNELS (NUM_OF_CHANNELS),
.MAX_CHANNELS (MAX_CHANNELS),
.SEL_CHANNELS ((n+1)))
i_dsf (
.dac_clk (dac_clk),
.dac_valid (dac_valid_s),
.dac_data (dac_data),
.dac_dmx_enable (dac_dmx_enable_m_s[n]),
.dac_dsf_req (dac_dsf_req_s[n]),
.dac_dsf_sync (dac_dsf_sync_s[n]),
.dac_dsf_valid (dac_dsf_valid_s[n]),
.dac_dsf_data (dac_dsf_data_s[n]));
end
// demux
for (n = 0; n < (CHANNEL_DATA_WIDTH/16); n = n + 1) begin: g_dmx
util_upack_dmx i_dmx (
.dac_clk (dac_clk),
.dac_enable (dac_enable_s),
.dac_valid (dac_dmx_valid_s[n]),
.dac_data_0 (dac_data_0[((16*n)+15):(16*n)]),
.dac_data_1 (dac_data_1[((16*n)+15):(16*n)]),
.dac_data_2 (dac_data_2[((16*n)+15):(16*n)]),
.dac_data_3 (dac_data_3[((16*n)+15):(16*n)]),
.dac_data_4 (dac_data_4[((16*n)+15):(16*n)]),
.dac_data_5 (dac_data_5[((16*n)+15):(16*n)]),
.dac_data_6 (dac_data_6[((16*n)+15):(16*n)]),
.dac_data_7 (dac_data_7[((16*n)+15):(16*n)]),
.dac_dmx_enable ({dac_dmx_enable_7_s[n], dac_dmx_enable_6_s[n],
dac_dmx_enable_5_s[n], dac_dmx_enable_4_s[n], dac_dmx_enable_3_s[n],
dac_dmx_enable_2_s[n], dac_dmx_enable_1_s[n], dac_dmx_enable_0_s[n]}),
.dac_dsf_valid (dac_dsf_valid_m_s),
.dac_dsf_data (dac_dsf_data_m_s[((MAX_CHANNELS*16*(n+1))-1):(MAX_CHANNELS*16*n)]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

3645
library/util_upack/util_upack_dmx.v
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238
library/util_upack/util_upack_dsf.v
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@ -1,238 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_upack_dsf #(
parameter CHANNEL_DATA_WIDTH = 32,
parameter NUM_OF_CHANNELS = 4,
parameter MAX_CHANNELS = 8,
parameter SEL_CHANNELS = 4) (
// dac interface
input dac_clk,
input dac_valid,
input [((CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS)-1):0] dac_data,
// dmx interface
input dac_dmx_enable,
output dac_dsf_req,
output dac_dsf_sync,
output dac_dsf_valid,
output [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data);
// internal parameters
localparam INT_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS;
localparam MAX_WIDTH = CHANNEL_DATA_WIDTH*MAX_CHANNELS;
localparam SEL_WIDTH = CHANNEL_DATA_WIDTH*SEL_CHANNELS;
localparam EXT_WIDTH = CHANNEL_DATA_WIDTH*(MAX_CHANNELS+1);
// internal registers
reg dac_valid_d1 = 'd0;
reg dac_dsf_req_d1 = 'd0;
reg dac_dsf_sync_d1 = 'd0;
reg dac_valid_d2 = 'd0;
reg dac_valid_d4 = 'd0;
reg [(MAX_WIDTH-1):0] dac_data_d4 = 'd0;
// internal signals
wire [ 2:0] dac_samples_i_s;
wire [ 2:0] dac_samples_s;
wire [(EXT_WIDTH-1):0] dac_data_d2_s;
wire [(EXT_WIDTH-1):0] dac_data_i_d2_0_s;
wire [(EXT_WIDTH-1):0] dac_data_i_d2_1_s;
wire [(MAX_WIDTH-1):0] dac_data_d3_s;
// bypass (all channels selected)
genvar i;
generate
if (SEL_CHANNELS == NUM_OF_CHANNELS) begin
assign dac_dsf_req = dac_dsf_req_d1;
assign dac_dsf_sync = dac_dsf_sync_d1;
assign dac_dsf_valid = dac_valid_d4;
assign dac_dsf_data = dac_data_d4;
assign dac_samples_i_s = 3'd0;
assign dac_samples_s = 'd0;
always @(posedge dac_clk) begin
dac_valid_d1 <= dac_valid & dac_dmx_enable;
dac_dsf_req_d1 <= dac_valid & dac_dmx_enable;
dac_dsf_sync_d1 <= dac_valid & dac_dmx_enable;
end
assign dac_data_d2_s = 'd0;
assign dac_data_i_d2_0_s = 'd0;
assign dac_data_i_d2_1_s = 'd0;
always @(posedge dac_clk) begin
dac_valid_d2 <= dac_valid_d1;
end
for (i = 0; i < (CHANNEL_DATA_WIDTH/16); i = i +1) begin: g_dsf_data_0
assign dac_data_d3_s[(((i +1)*MAX_CHANNELS*16)-1):(i*MAX_CHANNELS*16)] =
dac_data[(((i+1)*16*NUM_OF_CHANNELS)-1):(i*16*NUM_OF_CHANNELS)];
end
always @(posedge dac_clk) begin
if (dac_dmx_enable == 1'b1) begin
dac_valid_d4 <= dac_valid_d2;
dac_data_d4 <= dac_data_d3_s[(MAX_WIDTH-1):0];
end else begin
dac_valid_d4 <= 1'd0;
dac_data_d4 <= 'd0;
end
end
end
endgenerate
// data store & forward (not all channels selected)
generate
if (NUM_OF_CHANNELS > SEL_CHANNELS) begin
reg [ 2:0] dac_samples_d1 = 'd0;
reg dac_dsf_req_d2 = 'd0;
reg [ 2:0] dac_samples_d2 = 'd0;
reg dac_valid_d3 = 'd0;
reg [(MAX_WIDTH-1):0] dac_data_i_d3 = 'd0;
reg [(MAX_WIDTH-1):0] dac_data_d3 = 'd0;
assign dac_dsf_req = dac_dsf_req_d1;
assign dac_dsf_sync = dac_dsf_sync_d1;
assign dac_dsf_valid = dac_valid_d4;
assign dac_dsf_data = dac_data_d4;
assign dac_samples_i_s = (dac_valid_d1 == 1'b1) ? dac_samples_s : dac_samples_d1;
assign dac_samples_s = (dac_dsf_req_d1 == 1'b1) ? (dac_samples_d1+(NUM_OF_CHANNELS-SEL_CHANNELS)) :
((dac_samples_d1 >= SEL_CHANNELS) ? (dac_samples_d1-SEL_CHANNELS) : dac_samples_d1);
always @(posedge dac_clk) begin
dac_valid_d1 <= dac_valid & dac_dmx_enable;
if ((dac_dmx_enable == 1'b0) || (dac_samples_i_s >= SEL_CHANNELS)) begin
dac_dsf_req_d1 <= 1'b0;
end else begin
dac_dsf_req_d1 <= dac_valid;
end
if ((dac_dmx_enable == 1'b1) && (dac_samples_i_s == 3'd0)) begin
dac_dsf_sync_d1 <= 1'b0;
end else begin
dac_dsf_sync_d1 <= dac_valid;
end
if (dac_dmx_enable == 1'b0) begin
dac_samples_d1 <= 3'd0;
end else if (dac_valid_d1 == 1'b1) begin
dac_samples_d1 <= dac_samples_s;
end
end
assign dac_data_d2_s[(EXT_WIDTH-1):INT_WIDTH] = 'd0;
assign dac_data_d2_s[(INT_WIDTH-1):0] = dac_data;
assign dac_data_i_d2_0_s[(EXT_WIDTH-1):(EXT_WIDTH-INT_WIDTH)] = dac_data;
assign dac_data_i_d2_0_s[((EXT_WIDTH-INT_WIDTH)-1):0] =
dac_data_i_d3[(MAX_WIDTH-1):(MAX_WIDTH-(EXT_WIDTH-INT_WIDTH))];
assign dac_data_i_d2_1_s[(EXT_WIDTH-1):(EXT_WIDTH-(MAX_WIDTH-SEL_WIDTH))] =
dac_data_i_d3[(MAX_WIDTH-1):SEL_WIDTH];
assign dac_data_i_d2_1_s[((EXT_WIDTH-(MAX_WIDTH-SEL_WIDTH))-1):0] = 'd0;
always @(posedge dac_clk) begin
dac_valid_d2 <= dac_valid_d1;
dac_dsf_req_d2 <= dac_dsf_req_d1;
dac_samples_d2 <= dac_samples_d1;
end
always @(posedge dac_clk) begin
dac_valid_d3 <= dac_valid_d2;
if (dac_dsf_req_d2 == 1'b1) begin
dac_data_i_d3 <= dac_data_i_d2_0_s[(EXT_WIDTH-1):(EXT_WIDTH-MAX_WIDTH)];
end else if (dac_valid_d2 == 1'b1) begin
dac_data_i_d3 <= dac_data_i_d2_1_s[(EXT_WIDTH-1):(EXT_WIDTH-MAX_WIDTH)];
end
if (dac_valid_d2 == 1'b1) begin
case (dac_samples_d2)
3'b111: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*1)-1):0],
dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*1)]};
3'b110: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*2)-1):0],
dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*2)]};
3'b101: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*3)-1):0],
dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*3)]};
3'b100: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*4)-1):0],
dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*4)]};
3'b011: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*5)-1):0],
dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*5)]};
3'b010: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*6)-1):0],
dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*6)]};
3'b001: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*7)-1):0],
dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]};
3'b000: dac_data_d3 <= dac_data_d2_s;
default: dac_data_d3 <= 'd0;
endcase
end
end
for (i = 0; i < (CHANNEL_DATA_WIDTH/16); i = i + 1) begin: g_dsf_data_1
assign dac_data_d3_s[(((i+1)*MAX_CHANNELS*16)-1):(((i*MAX_CHANNELS)+SEL_CHANNELS)*16)] = 'd0;
assign dac_data_d3_s[((((i*MAX_CHANNELS)+SEL_CHANNELS)*16)-1):(i*MAX_CHANNELS*16)] =
dac_data_d3[(((i+1)*SEL_CHANNELS*16)-1):(i*SEL_CHANNELS*16)];
end
always @(posedge dac_clk) begin
if (dac_dmx_enable == 1'b1) begin
dac_valid_d4 <= dac_valid_d3;
dac_data_d4 <= dac_data_d3_s[(MAX_WIDTH-1):0];
end else begin
dac_valid_d4 <= 1'd0;
dac_data_d4 <= 'd0;
end
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

43
library/util_upack/util_upack_hw.tcl
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@ -1,43 +0,0 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
ad_ip_create util_upack {Channel Unpack Utility} util_upack_elab
ad_ip_files util_upack [list\
util_upack_dmx.v \
util_upack_dsf.v \
util_upack.v]
# parameters
ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 32
ad_ip_parameter NUM_OF_CHANNELS INTEGER 8
# defaults
ad_alt_intf clock dac_clk input 1
ad_alt_intf signal dac_valid output 1 valid
ad_alt_intf signal dac_sync output 1 sync
ad_alt_intf signal dac_data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data
for {set n 0} {$n < 8} {incr n} {
add_interface dac_ch_${n} conduit end
add_interface_port dac_ch_${n} dac_enable_${n} enable Input 1
add_interface_port dac_ch_${n} dac_valid_${n} valid Input 1
add_interface_port dac_ch_${n} dac_valid_out_${n} data_valid Output 1
add_interface_port dac_ch_${n} dac_data_${n} data Output CHANNEL_DATA_WIDTH
set_interface_property dac_ch_${n} associatedClock if_dac_clk
set_interface_property dac_ch_${n} associatedReset none
}
proc util_upack_elab {} {
set num_channels [get_parameter_value NUM_OF_CHANNELS]
for {set n 1} {$n < 8} {incr n} {
if {$n >= $num_channels} {
set_interface_property dac_ch_${n} ENABLED false
}
}
}

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library/util_upack/util_upack_ip.tcl
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@ -1,38 +0,0 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_upack
adi_ip_files util_upack [list \
"util_upack_dmx.v" \
"util_upack_dsf.v" \
"util_upack.v" ]
adi_ip_properties_lite util_upack
set_property driver_value 0 [ipx::get_ports *dac_enable* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_data* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
[ipx::get_ports *_1* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
[ipx::get_ports *_2* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \
[ipx::get_ports *_3* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \
[ipx::get_ports *_4* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \
[ipx::get_ports *_5* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \
[ipx::get_ports *_6* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
[ipx::get_ports *_7* -of_objects [ipx::current_core]]
ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]