axi_ad9963: updated tx path

- removed pll for power saving, added serdes circuitry instead

library/axi_ad9963/axi_ad9963.v

@@ -56,7 +56,7 @@ module axi_ad9963 #(
 
   // physical interface (transmit)
 
-  output          tx_clk,
+  input           tx_clk,
   output          tx_iq,
   output  [11:0]  tx_data,
 
@@ -145,9 +145,6 @@ module axi_ad9963 #(
   wire    [12:0]  up_adc_dld_s;
   wire    [64:0]  up_adc_dwdata_s;
   wire    [64:0]  up_adc_drdata_s;
-  wire    [13:0]  up_dac_dld_s;
-  wire    [69:0]  up_dac_dwdata_s;
-  wire    [69:0]  up_dac_drdata_s;
   wire            delay_locked_s;
   wire            up_wreq_s;
   wire    [13:0]  up_waddr_s;
@@ -161,6 +158,8 @@ module axi_ad9963 #(
   wire    [31:0]  up_rdata_tx_s;
   wire            up_rack_tx_s;
 
+  wire            dac_rst;
+
   // signal name changes
 
   assign up_clk = s_axi_aclk;
@@ -190,6 +189,7 @@ module axi_ad9963 #(
     .rst (rst),
     .l_clk (l_clk),
     .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
     .adc_valid (adc_valid_s),
     .adc_data (adc_data_s),
     .adc_status (adc_status_s),
@@ -199,9 +199,6 @@ module axi_ad9963 #(
     .up_adc_dld (up_adc_dld_s),
     .up_adc_dwdata (up_adc_dwdata_s),
     .up_adc_drdata (up_adc_drdata_s),
-    .up_dac_dld (up_dac_dld_s),
-    .up_dac_dwdata (up_dac_dwdata_s),
-    .up_dac_drdata (up_dac_drdata_s),
     .delay_clk (delay_clk),
     .delay_rst (delay_rst),
     .delay_locked (delay_locked_s));
@@ -249,12 +246,13 @@ module axi_ad9963 #(
     .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
   i_tx (
     .dac_clk (dac_clk),
+    .dac_rst (dac_rst),
     .dac_valid (dac_valid_s),
     .dac_data (dac_data_s),
     .adc_data (adc_data_s),
-    .up_dld (up_dac_dld_s),
+    .up_dld (),
-    .up_dwdata (up_dac_dwdata_s),
+    .up_dwdata (),
-    .up_drdata (up_dac_drdata_s),
+    .up_drdata (69'h0),
     .delay_clk (delay_clk),
     .delay_rst (),
     .delay_locked (delay_locked_s),

library/axi_ad9963/axi_ad9963_if.v

@@ -46,7 +46,7 @@ module axi_ad9963_if #(
 
   // physical interface (transmit)
 
-  output              tx_clk,
+  input               tx_clk,
   output              tx_iq,
   output      [11:0]  tx_data,
 
@@ -55,6 +55,7 @@ module axi_ad9963_if #(
   input               rst,
   output              l_clk,
   output              dac_clk,
+  input               dac_rst,
 
   // receive data path interface
 
@@ -73,9 +74,6 @@ module axi_ad9963_if #(
   input   [12:0]  up_adc_dld,
   input   [64:0]  up_adc_dwdata,
   output  [64:0]  up_adc_drdata,
-  input   [13:0]  up_dac_dld,
-  input   [69:0]  up_dac_dwdata,
-  output  [69:0]  up_dac_drdata,
   input           delay_clk,
   input           delay_rst,
   output          delay_locked);
@@ -85,8 +83,6 @@ module axi_ad9963_if #(
   reg     [11:0]  rx_data_p = 0;
   reg     [11:0]  tx_data_p = 'd0;
   reg     [11:0]  tx_data_n = 'd0;
-  reg             tx_n_iq = 'd0;
-  reg             tx_p_iq = 'd0;
 
   // internal signals
 
@@ -95,8 +91,8 @@ module axi_ad9963_if #(
   wire            rx_iq_p_s;
   wire            rx_iq_n_s;
 
-  wire            feedback_clk;
+  wire            tx_clk_serdes;
-  wire            tx_clk_pll;
+  wire            div_clk;
 
   genvar          l_inst;
 
@@ -115,8 +111,6 @@ module axi_ad9963_if #(
     if(dac_valid == 1'b1) begin
       tx_data_p   <= dac_data[11:0] ;
       tx_data_n   <= dac_data[23:12];
-      tx_p_iq     <= 1'b1;
-      tx_n_iq     <= 1'b0;
     end
   end
 
@@ -180,116 +174,58 @@ module axi_ad9963_if #(
     .delay_rst (delay_rst),
     .delay_locked (delay_locked));
 
-  // transmit data interface, oddr -> obuf
+  // transmit data interface
 
-  generate
+  BUFG dac_bufg (
-  for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
+    .I(div_clk),
-  ad_lvds_out #(
+    .O(dac_clk));
+
+  ad_serdes_clk #(
+    .DEVICE_TYPE(DEVICE_TYPE),
+    .DDR_OR_SDR_N(0),
+    .MMCM_OR_BUFR_N (1'b0),
+    .CLKIN_DS_OR_SE_N(0),
+    .SERDES_FACTOR(2)) 
+  tx_serdes_clk (
+    .rst(1'b0),
+    .clk_in_p(tx_clk),
+    .clk_in_n(1'b0),
+    .clk(tx_clk_serdes),
+    .div_clk(div_clk),
+    .out_clk(),
+    .loaden(),
+    .phase(),
+    .up_clk(1'b0),
+    .up_rstn(1'b0),
+    .up_drp_sel(1'b0),
+    .up_drp_wr(1'b0),
+    .up_drp_addr(12'h0),
+    .up_drp_wdata(32'h0),
+    .up_drp_rdata(),
+    .up_drp_ready(),
+    .up_drp_locked());
+
+  ad_serdes_out #(
     .DEVICE_TYPE (DEVICE_TYPE),
-    .SINGLE_ENDED (1),
+    .DDR_OR_SDR_N (1'b0),
-    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
+    .SERDES_FACTOR(2),
-    .IODELAY_CTRL (0),
+    .DATA_WIDTH (13))
-    .IODELAY_GROUP (IO_DELAY_GROUP))
+  i_serdes_out_data (
-  i_tx_data (
+    .rst (dac_rst),
-    .tx_clk (dac_clk),
+    .clk (tx_clk_serdes),
-    .tx_data_p (tx_data_p[l_inst]),
+    .div_clk (div_clk),
-    .tx_data_n (tx_data_n[l_inst]),
+    .loaden (1'b0),
-    .tx_data_out_p (tx_data[l_inst]),
+    .data_s0 ({1'b1,tx_data_p}),
-    .tx_data_out_n (),
+    .data_s1 ({1'b0,tx_data_n}),
-    .up_clk (up_clk),
+    .data_s2 (13'h0),
-    .up_dld (up_dac_dld[l_inst]),
+    .data_s3 (13'h0),
-    .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
+    .data_s4 (13'h0),
-    .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
+    .data_s5 (13'h0),
-    .delay_clk (delay_clk),
+    .data_s6 (13'h0),
-    .delay_rst (delay_rst),
+    .data_s7 (13'h0),
-    .delay_locked ());
+    .data_out_se ({tx_iq,tx_data}),
-  end
+    .data_out_p (),
-  endgenerate
+    .data_out_n ());
-
-  // transmit iq interface, oddr -> obuf
-
-  ad_lvds_out #(
-    .DEVICE_TYPE (DEVICE_TYPE),
-    .SINGLE_ENDED (1),
-    .IODELAY_ENABLE (DAC_IODELAY_ENABLE),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP))
-  i_tx_iq (
-    .tx_clk (dac_clk),
-    .tx_data_p (tx_p_iq),
-    .tx_data_n (tx_n_iq),
-    .tx_data_out_p (tx_iq),
-    .tx_data_out_n (),
-    .up_clk (up_clk),
-    .up_dld (up_dac_dld[12]),
-    .up_dwdata (up_dac_dwdata[64:60]),
-    .up_drdata (up_dac_drdata[64:60]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
-
-  // transmit clock interface, oddr -> obuf
-  PLLE2_BASE #(
-    .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
-    .CLKFBOUT_MULT(15), // Multiply value for all CLKOUT, (2-64)
-    .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
-    .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-    // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
-    .CLKOUT0_DIVIDE(20),
-    .CLKOUT1_DIVIDE(20),
-    .CLKOUT2_DIVIDE(1),
-    .CLKOUT3_DIVIDE(1),
-    .CLKOUT4_DIVIDE(1),
-    .CLKOUT5_DIVIDE(1),
-    // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
-    .CLKOUT0_DUTY_CYCLE(0.5),
-    .CLKOUT1_DUTY_CYCLE(0.5),
-    .CLKOUT2_DUTY_CYCLE(0.5),
-    .CLKOUT3_DUTY_CYCLE(0.5),
-    .CLKOUT4_DUTY_CYCLE(0.5),
-    .CLKOUT5_DUTY_CYCLE(0.5),
-    // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
-    .CLKOUT0_PHASE(90.0),
-    .CLKOUT1_PHASE(0.0),
-    .CLKOUT2_PHASE(0.0),
-    .CLKOUT3_PHASE(0.0),
-    .CLKOUT4_PHASE(0.0),
-    .CLKOUT5_PHASE(0.0),
-    .DIVCLK_DIVIDE(1), // Master division value, (1-56)
-    .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
-    .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
-    )
-    PLLE2_BASE_inst (
-    // Clock Outputs: 1-bit (each) output: User configurable clock outputs
-    .CLKOUT0(tx_clk_pll), // 1-bit output: CLKOUT0
-    .CLKOUT1(dac_clk), // 1-bit output: CLKOUT1
-    .CLKOUT2(), // 1-bit output: CLKOUT2
-    .CLKOUT3(), // 1-bit output: CLKOUT3
-    .CLKOUT4(), // 1-bit output: CLKOUT4
-    .CLKOUT5(), // 1-bit output: CLKOUT5
-    // Feedback Clocks: 1-bit (each) output: Clock feedback ports
-    .CLKFBOUT(feedback_clk), // 1-bit output: Feedback clock
-    .LOCKED(), // 1-bit output: LOCK
-    .CLKIN1(l_clk), // 1-bit input: Input clock
-    // Control Ports: 1-bit (each) input: PLL control ports
-    .PWRDWN(1'b0), // 1-bit input: Power-down
-    .RST(rst), // 1-bit input: Reset
-    // Feedback Clocks: 1-bit (each) input: Clock feedback ports
-    .CLKFBIN(feedback_clk) // 1-bit input: Feedback clock
-    );
-
-  ODDR #(
-    .DDR_CLK_EDGE ("SAME_EDGE"),
-    .INIT (1'b0),
-    .SRTYPE ("ASYNC"))
-  i_tx_clk_oddr(
-    .CE (1'b1),
-    .R (1'b0),
-    .S (1'b0),
-    .C (tx_clk_pll),
-    .D1 (1'b1),
-    .D2 (1'b0),
-    .Q (tx_clk));
 
 endmodule
 

library/axi_ad9963/axi_ad9963_ip.tcl

@@ -11,7 +11,8 @@ adi_ip_files axi_ad9963 [list \
   "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
   "$ad_hdl_dir/library/common/ad_rst.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \
-  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/ad_dds_sine.v" \

library/axi_ad9963/axi_ad9963_tx.v

@@ -47,6 +47,7 @@ module axi_ad9963_tx #(
   // dac interface
 
   input               dac_clk,
+  output              dac_rst,
   output reg          dac_valid,
   output      [23:0]  dac_data,
   input       [23:0]  adc_data,
@@ -94,10 +95,6 @@ module axi_ad9963_tx #(
   reg             dac_data_sync = 'd0;
   reg     [ 7:0]  dac_rate_cnt = 'd0;
 
-  // internal clock and resets
-
-  wire            dac_rst;
-
   // internal signals
 
   wire            dac_data_sync_s;

library/axi_ad9963/axi_ad9963_tx_channel.v

@@ -114,122 +114,6 @@ module axi_ad9963_tx_channel #(
   wire    [15:0]  dac_iqcor_coeff_1_s;
   wire    [15:0]  dac_iqcor_coeff_2_s;
 
-  // standard prbs functions
-
-  function [23:0] pn1fn;
-    input [23:0] din;
-    reg   [23:0] dout;
-    begin
-      case (PRBS_SEL)
-        PRBS_P09: begin
-          dout[23] = din[ 8] ^ din[ 4];
-          dout[22] = din[ 7] ^ din[ 3];
-          dout[21] = din[ 6] ^ din[ 2];
-          dout[20] = din[ 5] ^ din[ 1];
-          dout[19] = din[ 4] ^ din[ 0];
-          dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
-          dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
-          dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
-          dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
-          dout[14] = din[ 8] ^ din[ 0];
-          dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
-          dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
-          dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
-          dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
-          dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
-          dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
-          dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
-          dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
-          dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
-          dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
-          dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
-          dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
-          dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
-          dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
-        end
-        PRBS_P11: begin
-          dout[23] = din[10] ^ din[ 8];
-          dout[22] = din[ 9] ^ din[ 7];
-          dout[21] = din[ 8] ^ din[ 6];
-          dout[20] = din[ 7] ^ din[ 5];
-          dout[19] = din[ 6] ^ din[ 4];
-          dout[18] = din[ 5] ^ din[ 3];
-          dout[17] = din[ 4] ^ din[ 2];
-          dout[16] = din[ 3] ^ din[ 1];
-          dout[15] = din[ 2] ^ din[ 0];
-          dout[14] = din[ 1] ^ din[10] ^ din[ 8];
-          dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
-          dout[12] = din[10] ^ din[ 6];
-          dout[11] = din[ 9] ^ din[ 5];
-          dout[10] = din[ 8] ^ din[ 4];
-          dout[ 9] = din[ 7] ^ din[ 3];
-          dout[ 8] = din[ 6] ^ din[ 2];
-          dout[ 7] = din[ 5] ^ din[ 1];
-          dout[ 6] = din[ 4] ^ din[ 0];
-          dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
-          dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
-          dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
-          dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
-          dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
-          dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
-        end
-        PRBS_P15: begin
-          dout[23] = din[14] ^ din[13];
-          dout[22] = din[13] ^ din[12];
-          dout[21] = din[12] ^ din[11];
-          dout[20] = din[11] ^ din[10];
-          dout[19] = din[10] ^ din[ 9];
-          dout[18] = din[ 9] ^ din[ 8];
-          dout[17] = din[ 8] ^ din[ 7];
-          dout[16] = din[ 7] ^ din[ 6];
-          dout[15] = din[ 6] ^ din[ 5];
-          dout[14] = din[ 5] ^ din[ 4];
-          dout[13] = din[ 4] ^ din[ 3];
-          dout[12] = din[ 3] ^ din[ 2];
-          dout[11] = din[ 2] ^ din[ 1];
-          dout[10] = din[ 1] ^ din[ 0];
-          dout[ 9] = din[ 0] ^ din[14] ^ din[13];
-          dout[ 8] = din[14] ^ din[12];
-          dout[ 7] = din[13] ^ din[11];
-          dout[ 6] = din[12] ^ din[10];
-          dout[ 5] = din[11] ^ din[ 9];
-          dout[ 4] = din[10] ^ din[ 8];
-          dout[ 3] = din[ 9] ^ din[ 7];
-          dout[ 2] = din[ 8] ^ din[ 6];
-          dout[ 1] = din[ 7] ^ din[ 5];
-          dout[ 0] = din[ 6] ^ din[ 4];
-        end
-        PRBS_P20: begin
-          dout[23] = din[19] ^ din[ 2];
-          dout[22] = din[18] ^ din[ 1];
-          dout[21] = din[17] ^ din[ 0];
-          dout[20] = din[16] ^ din[19] ^ din[ 2];
-          dout[19] = din[15] ^ din[18] ^ din[ 1];
-          dout[18] = din[14] ^ din[17] ^ din[ 0];
-          dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
-          dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
-          dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
-          dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
-          dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
-          dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
-          dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
-          dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
-          dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
-          dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
-          dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
-          dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
-          dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
-          dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
-          dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
-          dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
-          dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
-          dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
-        end
-      endcase
-      pn1fn = dout;
-    end
-  endfunction
-
   // global toggle
 
   always @(posedge dac_clk) begin
@@ -271,8 +155,6 @@ module axi_ad9963_tx_channel #(
 
   always @(posedge dac_clk) begin
     case (dac_data_sel_s)
-      4'h9: dac_data_out <= dac_pn_data;
-      4'h8: dac_data_out <= 16'h0;
       4'h6: dac_data_out <= dac_test_data[11:0];
       4'h5: dac_data_out <= dac_data_out-1;
       4'h4: dac_data_out <= dac_data_out+1;
@@ -304,23 +186,6 @@ module axi_ad9963_tx_channel #(
     end
   end
 
-  // prbs sequences
-
-  always @(posedge dac_clk) begin
-    if (dac_data_sync == 1'b1) begin
-      dac_pn_seq <= 24'hffffff;
-      dac_pn_data <= 12'd0;
-    end else if (dac_valid == 1'b1) begin
-      if (dac_valid_sel == 1'b1) begin
-        dac_pn_seq <= pn1fn(dac_pn_seq);
-        dac_pn_data <= dac_pn_seq[11: 0];
-      end else begin
-        dac_pn_seq <= dac_pn_seq;
-        dac_pn_data <= dac_pn_seq[23:12];
-      end
-    end
-  end
-
   // pattern
 
   always @(posedge dac_clk) begin
@@ -335,6 +200,11 @@ module axi_ad9963_tx_channel #(
 
   // dds
 
+  generate
+  if (DATAPATH_DISABLE == 1) begin
+  assign dac_dds_data_s = 16'd0;
+  end else begin
+
   always @(posedge dac_clk) begin
     if (dac_data_sync == 1'b1) begin
       dac_dds_phase_0 <= dac_dds_init_1_s;
@@ -351,12 +221,6 @@ module axi_ad9963_tx_channel #(
     end
   end
 
-  // dds
-
-  generate
-  if (DATAPATH_DISABLE == 1) begin
-  assign dac_dds_data_s = 16'd0;
-  end else begin
   ad_dds i_dds (
     .clk (dac_clk),
     .dds_format (dac_dds_format),