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axi_logic_analyzer: Streaming flag initial commit 

If the streaming bit is set, after the trigger condition is met
data will be continuosly captured by the DMA. The streaming bit
must be set to 0 to reset triggering.
main
Adrian Costina 2017-07-03 18:00:23 +03:00
parent 99e8aa385a
commit 9f8a94df69
2 changed files with 37 additions and 5 deletions
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24
library/axi_logic_analyzer/axi_logic_analyzer.v
View File

@ -106,6 +106,8 @@ module axi_logic_analyzer (
reg up_triggered_reset_d1; reg up_triggered_reset_d1;
reg up_triggered_reset_d2; reg up_triggered_reset_d2;
reg streaming_on;
// internal signals // internal signals
wire up_clk; wire up_clk;
@ -141,6 +143,8 @@ module axi_logic_analyzer (
wire [31:0] trigger_delay; wire [31:0] trigger_delay;
wire trigger_out_delayed; wire trigger_out_delayed;
wire streaming;
genvar i; genvar i;
// signal name changes // signal name changes
@ -148,9 +152,25 @@ module axi_logic_analyzer (
assign up_clk = s_axi_aclk; assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn; assign up_rstn = s_axi_aresetn;
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s : trigger_out_delayed; assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0; assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
always @(posedge clk_out) begin
if (trigger_delay == 0) begin
if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
streaming_on <= 1'b1;
end else if (streaming == 1'b0) begin
streaming_on <= 1'b0;
end
end else begin
if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_delayed == 1'b1) begin
streaming_on <= 1'b1;
end else if (streaming == 1'b0) begin
streaming_on <= 1'b0;
end
end
end
always @(posedge clk_out) begin always @(posedge clk_out) begin
if (sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin if (sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
up_triggered_set <= 1'b1; up_triggered_set <= 1'b1;
@ -310,6 +330,8 @@ module axi_logic_analyzer (
.triggered (up_triggered), .triggered (up_triggered),
.streaming(streaming),
// bus interface // bus interface
.up_rstn (up_rstn), .up_rstn (up_rstn),

16
library/axi_logic_analyzer/axi_logic_analyzer_reg.v
View File

@ -60,6 +60,8 @@ module axi_logic_analyzer_reg (
input triggered, input triggered,
output streaming,
// bus interface // bus interface
input up_rstn, input up_rstn,
@ -94,6 +96,7 @@ module axi_logic_analyzer_reg (
reg [15:0] up_overwrite_data = 0; reg [15:0] up_overwrite_data = 0;
reg [15:0] up_od_pp_n = 0; reg [15:0] up_od_pp_n = 0;
reg up_triggered = 0; reg up_triggered = 0;
reg up_streaming = 0;
wire [15:0] up_input_data; wire [15:0] up_input_data;
@ -117,6 +120,7 @@ module axi_logic_analyzer_reg (
up_io_selection <= 16'h0; up_io_selection <= 16'h0;
up_od_pp_n <= 16'h0; up_od_pp_n <= 16'h0;
up_triggered <= 1'd0; up_triggered <= 1'd0;
up_streaming <= 1'd0;
end else begin end else begin
up_wack <= up_wreq; up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
@ -172,6 +176,9 @@ module axi_logic_analyzer_reg (
end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_triggered <= up_triggered & ~up_wdata[0]; up_triggered <= up_triggered & ~up_wdata[0];
end end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
up_streaming <= up_wdata[0];
end
end end
end end
@ -204,6 +211,7 @@ module axi_logic_analyzer_reg (
5'h10: up_rdata <= {16'h0,up_od_pp_n}; 5'h10: up_rdata <= {16'h0,up_od_pp_n};
5'h11: up_rdata <= up_trigger_delay; 5'h11: up_rdata <= up_trigger_delay;
5'h12: up_rdata <= {31'h0,up_triggered}; 5'h12: up_rdata <= {31'h0,up_triggered};
5'h13: up_rdata <= {31'h0,up_streaming};
default: up_rdata <= 0; default: up_rdata <= 0;
endcase endcase
end else begin end else begin
@ -214,10 +222,11 @@ module axi_logic_analyzer_reg (
ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset)); ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset));
up_xfer_cntrl #(.DATA_WIDTH(284)) i_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(285)) i_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_od_pp_n, // 16 .up_data_cntrl ({ up_streaming, // 1
up_od_pp_n, // 16
up_overwrite_data, // 16 up_overwrite_data, // 16
up_overwrite_enable, // 16 up_overwrite_enable, // 16
up_clock_select, // 1 up_clock_select, // 1
@ -236,7 +245,8 @@ module axi_logic_analyzer_reg (
.up_xfer_done (), .up_xfer_done (),
.d_rst (1'b0), .d_rst (1'b0),
.d_clk (clk), .d_clk (clk),
.d_data_cntrl ({ od_pp_n, // 16 .d_data_cntrl ({ streaming, // 1
od_pp_n, // 16
overwrite_data, // 16 overwrite_data, // 16
overwrite_enable, // 16 overwrite_enable, // 16
clock_select, // 1 clock_select, // 1