alt_serdes_clk- changes
Rejeesh Kutty
parent
f4be0524b4
commit
9e0c39a71b
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@ -1,229 +1,130 @@
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package require -exact qsys 13.0
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_alt.tcl
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package require -exact qsys 14.0
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set_module_property NAME util_serdes_clk
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set_module_property DESCRIPTION "A simple Altera IOPLL macro instance"
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set_module_property NAME alt_serdes
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set_module_property DESCRIPTION "Altera SERDES"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_serdes_clk
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set_module_property ELABORATION_CALLBACK p_util_serdes_clk
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set_module_property DISPLAY_NAME alt_serdes
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set_module_property COMPOSITION_CALLBACK p_alt_serdes
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add_fileset quartus_synth QUARTUS_SYNTH "" ""
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set_fileset_property quartus_synth TOP_LEVEL ad_serdes_clk
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add_fileset_file ad_serdes_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v TOP_LEVEL_FILE
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# parameters
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
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set_parameter_property DEVICE_FAMILY ENABLED false
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add_parameter MODE STRING 0
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set_parameter_property MODE DEFAULT_VALUE "TX"
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add_parameter MODE STRING "CLK"
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set_parameter_property MODE DISPLAY_NAME MODE
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set_parameter_property MODE TYPE STRING
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set_parameter_property MODE UNITS None
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set_parameter_property MODE HDL_PARAMETER true
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set_parameter_property MODE HDL_PARAMETER false
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set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "OUT"}
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add_hdl_instance alt_clk altera_iopll
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set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {500.0}
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set_instance_parameter_value alt_clk {gui_use_locked} {1}
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set_instance_parameter_value alt_clk {gui_operation_mode} {lvds}
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set_instance_parameter_value alt_clk {gui_en_lvds_ports} {true}
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set_instance_parameter_value alt_clk {gui_number_of_clocks} {4}
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set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {1200.0}
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set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
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set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value alt_clk {gui_duty_cycle0} {50.0}
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set_instance_parameter_value alt_clk {gui_output_clock_frequency1} {150.0}
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set_instance_parameter_value alt_clk {gui_ps_units1} {degrees}
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set_instance_parameter_value alt_clk {gui_phase_shift_deg1} {315.0}
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set_instance_parameter_value alt_clk {gui_duty_cycle1} {12.5}
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set_instance_parameter_value alt_clk {gui_output_clock_frequency2} {150.0}
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set_instance_parameter_value alt_clk {gui_ps_units2} {degrees}
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set_instance_parameter_value alt_clk {gui_phase_shift_deg2} {22.5}
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set_instance_parameter_value alt_clk {gui_duty_cycle2} {50.0}
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set_instance_parameter_value alt_clk {gui_output_clock_frequency3} {600.0}
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set_instance_parameter_value alt_clk {gui_ps_units3} {degrees}
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set_instance_parameter_value alt_clk {gui_phase_shift_deg3} {90}
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set_instance_parameter_value alt_clk {gui_duty_cycle3} {50.0}
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set_instance_parameter_value alt_clk {system_info_device_family} DEVICE_FAMILY
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set_instance_parameter_value alt_clk {gui_en_reconf} {true}
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add_parameter DDR_OR_SDR_N INTEGER 1
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set_parameter_property DDR_OR_SDR_N DISPLAY_NAME DDR_OR_SDR_N
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set_parameter_property DDR_OR_SDR_N TYPE INTEGER
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set_parameter_property DDR_OR_SDR_N UNITS None
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set_parameter_property DDR_OR_SDR_N HDL_PARAMETER false
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set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
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# input clock and reset
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add_parameter SERDES_FACTOR INTEGER 8
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set_parameter_property SERDES_FACTOR DISPLAY_NAME SERDES_FACTOR
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set_parameter_property SERDES_FACTOR TYPE INTEGER
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set_parameter_property SERDES_FACTOR UNITS None
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set_parameter_property SERDES_FACTOR HDL_PARAMETER false
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set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
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ad_alt_intf clock clk Output 1
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ad_alt_intf clock div_clk Output 1
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ad_alt_intf clock loaden Output 1
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add_parameter CLKIN_FREQUENCY FLOAT 500.0
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set_parameter_property CLKIN_FREQUENCY DISPLAY_NAME CLKIN_FREQUENCY
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set_parameter_property CLKIN_FREQUENCY TYPE FLOAT
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set_parameter_property CLKIN_FREQUENCY UNITS None
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set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
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set_parameter_property CLKIN_FREQUENCY HDL_PARAMETER false
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add_interface serdes_clk clock end
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add_interface_port serdes_clk clk_in_p clk Input 1
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proc p_alt_serdes {} {
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add_interface serdes_rst reset end
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set_interface_property serdes_rst associatedClock serdes_clk
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add_interface_port serdes_rst mmcm_rst reset Input 1
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set m_mode [get_parameter_value "MODE"]
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set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
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set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
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set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
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# updates
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proc p_util_serdes_clk {} {
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set serdes_clk_mode [get_parameter_value MODE]
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if {$serdes_clk_mode eq "TX"} {
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set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
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} elseif {$serdes_clk_mode eq "RX"} {
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set_instance_parameter_value alt_clk {gui_en_phout_ports} {true}
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ad_alt_intf signal phase Output 8
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} else {
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set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
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set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
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set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
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set m_ls_phase 315.0
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if {$m_serdes_factor == 4} {
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set m_ls_phase 270.0
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}
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if {$m_mode == "CLK"} {
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add_instance alt_serdes_pll altera_iopll
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set_instance_parameter_value alt_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
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set_instance_parameter_value alt_serdes_pll {gui_use_locked} {1}
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set_instance_parameter_value alt_serdes_pll {gui_operation_mode} {lvds}
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set_instance_parameter_value alt_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
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set_instance_parameter_value alt_serdes_pll {gui_en_phout_ports} {true}
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set_instance_parameter_value alt_serdes_pll {gui_en_reconf} {true}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units0} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units1} {degrees}
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set_instance_parameter_value alt_serdes_pll {gui_phase_shift_deg1} $m_ls_phase
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set_instance_parameter_value alt_serdes_pll {gui_duty_cycle1} {12.5}
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set_instance_parameter_value alt_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
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set_instance_parameter_value alt_serdes_pll {gui_ps_units2} {degrees}
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add_interface rst reset sink
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set_interface_property rst EXPORT_OF alt_serdes_pll.reset
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF alt_serdes_pll.refclk
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF alt_serdes_pll.locked
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF alt_serdes_pll.phout
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add_interface hs_clk conduit end
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set_interface_property hs_clk EXPORT_OF alt_serdes_pll.lvds_clk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF alt_serdes_pll.loaden
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add_interface ls_clk clock source
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set_interface_property ls_clk EXPORT_OF alt_serdes_pll.outclk2
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add_instance alt_serdes_pll_reconfig altera_pll_reconfig
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add_connection alt_serdes_pll.reconfig_from_pll alt_serdes_pll_reconfig.reconfig_from_pll
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add_connection alt_serdes_pll_reconfig.reconfig_to_pll alt_serdes_pll.reconfig_to_pll
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add_interface drp_clk clock sink
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set_interface_property drp_clk EXPORT_OF alt_serdes_pll_reconfig.mgmt_clk
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add_interface drp_rstn reset sink
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set_interface_property drp_rstn EXPORT_OF alt_serdes_pll_reconfig.mgmt_reset
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add_interface pll_reconfig avalon slave
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set_interface_property pll_reconfig EXPORT_OF alt_serdes_pll_reconfig.mgmt_avalon_slave
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}
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if {$m_mode == "IN"} {
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add_hdl_instance alt_serdes_in altera_lvds
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set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0}
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set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
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set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
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set_instance_parameter_value alt_serdes_in {J_FACTOR} {8}
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set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100}
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set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
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set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false}
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set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false}
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set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
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}
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if {$m_mode == "OUT"} {
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add_hdl_instance alt_serdes_out altera_lvds
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set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0}
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set_instance_parameter_value alt_serdes_out {MODE} {TX}
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set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
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set_instance_parameter_value alt_serdes_out {J_FACTOR} {8}
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set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100}
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set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
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set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
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set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
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set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
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}
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}
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package require -exact qsys 13.0
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_alt.tcl
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set_module_property NAME util_serdes_in
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set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in rx mode"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_serdes_in
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add_fileset quartus_synth QUARTUS_SYNTH "" ""
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set_fileset_property quartus_synth TOP_LEVEL ad_serdes_in
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add_fileset_file ad_serdes_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v TOP_LEVEL_FILE
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
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set_parameter_property DEVICE_FAMILY ENABLED false
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add_parameter DATA_WIDTH STRING
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set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
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set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
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set_parameter_property DATA_WIDTH TYPE INTEGER
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set_parameter_property DATA_WIDTH UNITS None
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set_parameter_property DATA_WIDTH HDL_PARAMETER true
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add_hdl_instance alt_serdes_in altera_lvds
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set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0}
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set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
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set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
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set_instance_parameter_value alt_serdes_in {J_FACTOR} {8}
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set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100}
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set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
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set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false}
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set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false}
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set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
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# input clock and reset
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add_interface fast_clk clock end
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add_interface_port fast_clk clk clk Input 1
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set_interface_property fast_clk associatedReset serdes_rst
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add_interface serdes_rst reset end
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add_interface_port serdes_rst rst reset Input 1
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set_interface_property serdes_rst associatedClock fast_clk
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add_interface div_clk clock end
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add_interface_port div_clk div_clk clk Input 1
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set_interface_property div_clk associatedReset none
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add_interface loaden clock end
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add_interface_port loaden loaden clk Input 1
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set_interface_property loaden associatedReset none
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add_interface parallel_data conduit end
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add_interface_port parallel_data data_s0 data0 output DATA_WIDTH
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add_interface_port parallel_data data_s1 data1 output DATA_WIDTH
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add_interface_port parallel_data data_s2 data2 output DATA_WIDTH
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add_interface_port parallel_data data_s3 data3 output DATA_WIDTH
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add_interface_port parallel_data data_s4 data4 output DATA_WIDTH
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add_interface_port parallel_data data_s5 data5 output DATA_WIDTH
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add_interface_port parallel_data data_s6 data6 output DATA_WIDTH
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add_interface_port parallel_data data_s7 data7 output DATA_WIDTH
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set_interface_property parallel_data associatedClock div_clk
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set_interface_property parallel_data associatedReset none
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add_interface serial_data conduit end
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add_interface_port serial_data data_out_p data_p output 1
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add_interface_port serial_data data_out_n data_n output 1
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package require -exact qsys 13.0
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_ip_alt.tcl
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set_module_property NAME util_serdes_out
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set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in tx mode"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_serdes_out
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add_fileset quartus_synth QUARTUS_SYNTH "" ""
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set_fileset_property quartus_synth TOP_LEVEL ad_serdes_out
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add_fileset_file ad_serdes_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v TOP_LEVEL_FILE
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
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set_parameter_property DEVICE_FAMILY ENABLED false
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add_parameter DATA_WIDTH STRING
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set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
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set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
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set_parameter_property DATA_WIDTH TYPE INTEGER
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set_parameter_property DATA_WIDTH UNITS None
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set_parameter_property DATA_WIDTH HDL_PARAMETER true
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add_parameter DEVICE_TYPE STRING
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set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
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set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
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set_parameter_property DEVICE_TYPE TYPE INTEGER
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set_parameter_property DEVICE_TYPE UNITS None
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set_parameter_property DEVICE_TYPE HDL_PARAMETER true
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add_hdl_instance alt_serdes_out altera_lvds
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set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0}
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set_instance_parameter_value alt_serdes_out {MODE} {TX}
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set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
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set_instance_parameter_value alt_serdes_out {J_FACTOR} {8}
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set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100}
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set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
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set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
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set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
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set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
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# input clock and reset
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ad_alt_intf clock clk Input 1
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ad_alt_intf clock div_clk Input 1
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ad_alt_intf clock loaden Input 1
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ad_alt_intf reset rst Input 1
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add_interface parallel_data conduit end
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add_interface_port parallel_data data_s0 data0 input DATA_WIDTH
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add_interface_port parallel_data data_s1 data1 input DATA_WIDTH
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add_interface_port parallel_data data_s2 data2 input DATA_WIDTH
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add_interface_port parallel_data data_s3 data3 input DATA_WIDTH
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add_interface_port parallel_data data_s4 data4 input DATA_WIDTH
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add_interface_port parallel_data data_s5 data5 input DATA_WIDTH
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add_interface_port parallel_data data_s6 data6 input DATA_WIDTH
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add_interface_port parallel_data data_s7 data7 input DATA_WIDTH
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set_interface_property parallel_data associatedClock div_clk
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set_interface_property parallel_data associatedReset none
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add_interface serial_data conduit end
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add_interface_port serial_data data_out_p data_p output 1
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add_interface_port serial_data data_out_n data_n output 1
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@ -42,98 +42,114 @@ module ad_serdes_clk (
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// clock and divided clock
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mmcm_rst,
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clk_in_p,
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clk_in_n,
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input rst,
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input clk_in_p,
|
||||
input clk_in_n,
|
||||
|
||||
clk,
|
||||
div_clk,
|
||||
out_clk,
|
||||
loaden,
|
||||
phase,
|
||||
output clk,
|
||||
output div_clk,
|
||||
output out_clk,
|
||||
output loaden,
|
||||
output [ 7:0] phase,
|
||||
|
||||
// drp interface
|
||||
|
||||
up_clk,
|
||||
up_rstn,
|
||||
up_drp_sel,
|
||||
up_drp_wr,
|
||||
up_drp_addr,
|
||||
up_drp_wdata,
|
||||
up_drp_rdata,
|
||||
up_drp_ready,
|
||||
up_drp_locked);
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_drp_sel,
|
||||
input up_drp_wr,
|
||||
input [11:0] up_drp_addr,
|
||||
input [31:0] up_drp_wdata,
|
||||
output [31:0] up_drp_rdata,
|
||||
output up_drp_ready,
|
||||
output up_drp_locked);
|
||||
|
||||
// parameters
|
||||
// internal registers
|
||||
|
||||
parameter MODE = "TX";
|
||||
reg up_drp_sel_int = 'd0;
|
||||
reg up_drp_rd_int = 'd0;
|
||||
reg up_drp_wr_int = 'd0;
|
||||
reg [ 8:0] up_drp_addr_int = 'd0;
|
||||
reg [31:0] up_drp_wdata_int = 'd0;
|
||||
reg [31:0] up_drp_rdata_int = 'd0;
|
||||
reg up_drp_ready_int = 'd0;
|
||||
reg up_drp_locked_int_m = 'd0;
|
||||
reg up_drp_locked_int = 'd0;
|
||||
|
||||
// clock and divided clock
|
||||
// internal signals
|
||||
|
||||
input mmcm_rst;
|
||||
input clk_in_p;
|
||||
input clk_in_n;
|
||||
wire [31:0] up_drp_rdata_int_s,
|
||||
wire up_drp_busy_int_s;
|
||||
wire up_drp_locked_int_s;
|
||||
|
||||
output clk;
|
||||
output div_clk;
|
||||
output out_clk;
|
||||
output loaden;
|
||||
output [ 7:0] phase;
|
||||
// defaults
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_clk;
|
||||
input up_rstn;
|
||||
input up_drp_sel;
|
||||
input up_drp_wr;
|
||||
input [11:0] up_drp_addr;
|
||||
input [15:0] up_drp_wdata;
|
||||
output [15:0] up_drp_rdata;
|
||||
output up_drp_ready;
|
||||
output up_drp_locked;
|
||||
|
||||
wire locked;
|
||||
|
||||
// ground the unused outputs
|
||||
|
||||
assign up_drp_rdata = 15'b0;
|
||||
assign up_drp_ready = 1'b0;
|
||||
assign up_drp_locked = locked;
|
||||
|
||||
generate if (MODE == "TX") begin
|
||||
|
||||
assign phase = 8'h0;
|
||||
|
||||
alt_clk i_alt_clk (
|
||||
.locked (locked), // locked.export
|
||||
.outclk_0 (clk), // outclk0.clk
|
||||
.outclk_1 (loaden), // outclk1.clk
|
||||
.outclk_2 (div_clk), // outclk2.clk
|
||||
.outclk_3 (out_clk), // outclk3.clk
|
||||
.reconfig_from_pll (), // reconfig_from_pll.reconfig_from_pll
|
||||
.reconfig_to_pll (), // reconfig_to_pll.reconfig_to_pll
|
||||
.refclk (clk_in_p), // refclk.clk
|
||||
.rst (mmcm_rst) // reset.reset
|
||||
);
|
||||
|
||||
// TODO: Add Altera PLL Reconfig IP
|
||||
|
||||
end else begin
|
||||
|
||||
alt_clk i_alt_clk (
|
||||
.locked (locked), // locked.export
|
||||
.outclk_0 (clk), // outclk0.clk
|
||||
.outclk_1 (loaden), // outclk1.clk
|
||||
.outclk_2 (div_clk), // outclk2.clk
|
||||
.outclk_3 (out_clk), // outclk3.clk
|
||||
.reconfig_from_pll (), // reconfig_from_pll.reconfig_from_pll
|
||||
.reconfig_to_pll (), // reconfig_to_pll.reconfig_to_pll
|
||||
.phout (phase),
|
||||
.refclk (clk_in_p), // refclk.clk
|
||||
.rst (mmcm_rst) // reset.reset
|
||||
);
|
||||
assign out_clk = div_clk;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_drp_sel_int <= 1'b0;
|
||||
up_drp_rd_int <= 1'b0;
|
||||
up_drp_wr_int <= 1'b0;
|
||||
up_drp_addr_int <= 9'd0;
|
||||
up_drp_wdata_int <= 32'd0;
|
||||
up_drp_rdata_int <= 32'd0;
|
||||
up_drp_ready_int <= 1'b0;
|
||||
up_drp_locked_int_m <= 1'd0;
|
||||
up_drp_locked_int <= 1'd0;
|
||||
end else begin
|
||||
if (up_drp_sel_int == 1'b1) begin
|
||||
if (up_drp_busy_int_s == 1'b0) begin
|
||||
up_drp_sel_int <= 1'b0;
|
||||
up_drp_rd_int <= 1'b0;
|
||||
up_drp_wr_int <= 1'b0;
|
||||
up_drp_addr_int <= 9'd0;
|
||||
up_drp_wdata_int <= 32'd0;
|
||||
up_drp_rdata_int <= up_drp_rdata_int_s;
|
||||
up_drp_ready_int <= 1'b1;
|
||||
end
|
||||
end else if (up_drp_sel == 1'b1) begin
|
||||
up_drp_sel_int <= 1'b1;
|
||||
up_drp_rd_int <= ~up_drp_wr;
|
||||
up_drp_wr_int <= up_drp_wr;
|
||||
up_drp_addr_int <= up_drp_addr[8:0];
|
||||
up_drp_wdata_int <= up_drp_wdata;
|
||||
up_drp_rdata_int <= 32'd0;
|
||||
up_drp_ready_int <= 1'b0;
|
||||
end else begin
|
||||
up_drp_sel_int <= 1'b0;
|
||||
up_drp_rd_int <= 1'b0;
|
||||
up_drp_wr_int <= 1'b0;
|
||||
up_drp_addr_int <= 9'd0;
|
||||
up_drp_wdata_int <= 32'd0;
|
||||
up_drp_rdata_int <= 32'd0;
|
||||
up_drp_ready_int <= 1'b0;
|
||||
end
|
||||
up_drp_locked_int_m <= up_drp_locked_int_s;
|
||||
up_drp_locked_int <= up_drp_locked_int_m;
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// instantiations (ip- hw.tcl must generate this core)
|
||||
|
||||
alt_serdes_clk_core i_core (
|
||||
.rst_reset (rst),
|
||||
.ref_clk_clk (clk_in_p),
|
||||
.locked_export (up_drp_locked_int_s),
|
||||
.hs_phase_phout (phase),
|
||||
.hs_clk_lvds_clk (clk),
|
||||
.loaden_loaden (loaden),
|
||||
.ls_clk_clk (div_clk),
|
||||
.drp_clk_clk (up_clk),
|
||||
.drp_rstn_reset (up_rstn),
|
||||
.pll_reconfig_waitrequest (up_drp_busy_int_s),
|
||||
.pll_reconfig_read (up_drp_rd_int),
|
||||
.pll_reconfig_write (up_drp_wr_int),
|
||||
.pll_reconfig_readdata (up_drp_rdata_int_s),
|
||||
.pll_reconfig_address (up_drp_addr_int),
|
||||
.pll_reconfig_writedata (up_drp_wdata_int));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue