reset and clock additions
parent
897c31ebbf
commit
9d95ddc620
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@ -15,6 +15,41 @@ proc ad_alt_intf {type name dir width {remap ""}} {
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return
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}
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if {(($type eq "reset") && ($dir eq "input"))} {
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add_interface if_${name} reset sink
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add_interface_port if_${name} ${name} reset ${dir} ${width}
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set_interface_property if_${name} associatedclock if_${remap}
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return
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}
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if {(($type eq "reset") && ($dir eq "output"))} {
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add_interface if_${name} reset source
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add_interface_port if_${name} ${name} reset ${dir} ${width}
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set_interface_property if_${name} associatedclock if_${remap}
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return
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}
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if {(($type eq "reset-n") && ($dir eq "input"))} {
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add_interface if_${name} reset sink
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add_interface_port if_${name} ${name} reset_n ${dir} ${width}
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set_interface_property if_${name} associatedclock if_${remap}
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return
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}
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if {(($type eq "reset-n") && ($dir eq "output"))} {
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add_interface if_${name} reset source
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add_interface_port if_${name} ${name} reset_n ${dir} ${width}
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set_interface_property if_${name} associatedclock if_${remap}
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return
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}
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if {(($type eq "intr") && ($dir eq "output"))} {
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add_interface if_${name} interrupt source
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add_interface_port if_${name} ${name} irq ${dir} ${width}
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set_interface_property if_${name} associatedclock if_${remap}
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return
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}
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if {$remap eq ""} {
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set remap $name
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}
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