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library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register

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Filip Gherman 2022-01-11 17:58:42 +02:00 committed by Filip Gherman
parent fc04198b2b
commit 9d8097389c
1 changed files with 1 additions and 1 deletions
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library/jesd204/jesd204_common/pipeline_stage.v
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@ -59,7 +59,7 @@ generate if (REGISTERED == 0) begin
end else begin end else begin
(* shreg_extract = "no" *) reg [REGISTERED*WIDTH-1:0] in_dly; (* shreg_extract = "no" *) reg [REGISTERED*WIDTH-1:0] in_dly = {REGISTERED*WIDTH{1'b0}};
always @(posedge clk) in_dly <= {in_dly,in}; always @(posedge clk) in_dly <= {in_dly,in};