Merge branch 'master' of https://github.com/analogdevicesinc/hdl

2014-03-18 15:30:29 +02:00 · 2014-03-18 15:30:29 +02:00 · 9d65071235
parent 2c898bf3a2 f3c503cfb8
commit 9d65071235
10 changed files with 203 additions and 139 deletions
--- a/projects/adv7511/kc705/system_bd.tcl
+++ b/projects/adv7511/kc705/system_bd.tcl
@ -1,8 +1,4 @@

 source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
-set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
-set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
-set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
-set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc


--- a/projects/adv7511/kc705/system_top.v
+++ b/projects/adv7511/kc705/system_top.v
@ -202,7 +202,11 @@ module system_top (
    .sys_clk_p (sys_clk_p),
    .sys_rst (sys_rst),
    .uart_sin (uart_sin),
-    .uart_sout (uart_sout));
+    .uart_sout (uart_sout),
+    .unc_int0 (1'b0),
+    .unc_int1 (1'b0),
+    .unc_int2 (1'b0),
+    .unc_int3 (1'b0));

 endmodule

--- a/projects/common/kc705/kc705_system_bd.tcl
+++ b/projects/common/kc705/kc705_system_bd.tcl
@ -1,4 +1,7 @@

+# create board design
+# interface ports
+
 set sys_rst         [create_bd_port -dir I -type rst sys_rst]
 set sys_clk_p       [create_bd_port -dir I sys_clk_p]
 set sys_clk_n       [create_bd_port -dir I sys_clk_n]
@ -21,6 +24,11 @@ set iic_main        [create_bd_intf_port -mode Master -vlnv xilinx.com:interface
 set uart_sin        [create_bd_port -dir I uart_sin]
 set uart_sout       [create_bd_port -dir O uart_sout]

+set unc_int0        [create_bd_port -dir I unc_int0]
+set unc_int1        [create_bd_port -dir I unc_int1]
+set unc_int2        [create_bd_port -dir I unc_int2]
+set unc_int3        [create_bd_port -dir I unc_int3]
+
 set hdmi_out_clk    [create_bd_port -dir O hdmi_out_clk]
 set hdmi_hsync      [create_bd_port -dir O hdmi_hsync]
 set hdmi_vsync      [create_bd_port -dir O hdmi_vsync]
@ -96,8 +104,11 @@ set_property -dict [list CONFIG.CONST_VAL {1}] $sys_const_ddr3_1

 # instance: axi interconnect (lite)

+set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect]
+set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect
+
 set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
-set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
+set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect

 # instance: axi interconnect

@ -136,8 +147,12 @@ set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led
 set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
 set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc

+set sys_concat_aux_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_aux_intc]
+set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_aux_intc
+set_property -dict [list CONFIG.IN8_WIDTH {5}] $sys_concat_aux_intc
+
 set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
-set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc
+set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc

 # hdmi peripherals

@ -192,7 +207,8 @@ connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd

 connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG]
 connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
-connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr]
+connect_bd_net -net sys_concat_aux_intc_intr [get_bd_pins sys_concat_aux_intc/dout] [get_bd_pins axi_intc/intr]
+connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_concat_aux_intc/In7]

 # defaults (peripherals)

@ -208,8 +224,12 @@ connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source
 connect_bd_net -net sys_100m_clk $sys_100m_clk_source
 connect_bd_net -net sys_200m_clk $sys_200m_clk_source

+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_200m_resetn_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_100m_clk_source
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source
 connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_200m_clk_source

@ -240,41 +260,45 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]

 # defaults (interconnect - processor)

-connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m01 [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m02 [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_uart/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_timer/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_intc/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m06 [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_s00_axi [get_bd_intf_pins axi_cpu_aux_interconnect/S00_AXI] [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] 
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m00_axi [get_bd_intf_pins axi_cpu_aux_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m01_axi [get_bd_intf_pins axi_cpu_aux_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m03_axi [get_bd_intf_pins axi_cpu_aux_interconnect/M03_AXI] [get_bd_intf_pins axi_uart/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m04_axi [get_bd_intf_pins axi_cpu_aux_interconnect/M04_AXI] [get_bd_intf_pins axi_timer/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m05_axi [get_bd_intf_pins axi_cpu_aux_interconnect/M05_AXI] [get_bd_intf_pins axi_intc/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m06_axi [get_bd_intf_pins axi_cpu_aux_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m07_axi [get_bd_intf_pins axi_cpu_aux_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/S00_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M00_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M01_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M02_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M03_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M04_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M05_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M06_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M07_ACLK] $sys_100m_clk_source
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source

 # defaults (interconnect - memory)

-connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/S_AXI]
-connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
-connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
+connect_bd_intf_net -intf_net axi_mem_interconnect_m00_axi [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/S_AXI]
+connect_bd_intf_net -intf_net axi_mem_interconnect_s00_axi [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
+connect_bd_intf_net -intf_net axi_mem_interconnect_s01_axi [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
 connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_200m_resetn_source
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source
@ -290,12 +314,16 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sy

 # defaults (interrupts)

-connect_bd_net -net sys_concat_intc_intr_00 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt]
-connect_bd_net -net sys_concat_intc_intr_01 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/ip2intc_irpt]
-connect_bd_net -net sys_concat_intc_intr_02 [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_uart/interrupt]
-connect_bd_net -net sys_concat_intc_intr_03 [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
-connect_bd_net -net sys_concat_intc_intr_04 [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
-connect_bd_net -net sys_concat_intc_intr_05 [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_iic_main/iic2intc_irpt]
+connect_bd_net -net sys_concat_aux_intc_intr_00 [get_bd_pins sys_concat_aux_intc/In0] [get_bd_pins axi_timer/interrupt]
+connect_bd_net -net sys_concat_aux_intc_intr_01 [get_bd_pins sys_concat_aux_intc/In1] [get_bd_pins axi_ethernet/ip2intc_irpt]
+connect_bd_net -net sys_concat_aux_intc_intr_02 [get_bd_pins sys_concat_aux_intc/In2] [get_bd_ports unc_int0] 
+connect_bd_net -net sys_concat_aux_intc_intr_03 [get_bd_pins sys_concat_aux_intc/In3] [get_bd_pins axi_uart/interrupt]
+connect_bd_net -net sys_concat_aux_intc_intr_04 [get_bd_pins sys_concat_aux_intc/In4] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
+connect_bd_net -net sys_concat_aux_intc_intr_05 [get_bd_pins sys_concat_aux_intc/In5] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
+connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
+connect_bd_net -net sys_concat_intc_din_2 [get_bd_pins sys_concat_intc/In2] [get_bd_ports unc_int1]
+connect_bd_net -net sys_concat_intc_din_3 [get_bd_pins sys_concat_intc/In3] [get_bd_ports unc_int2]
+connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get_bd_ports unc_int3]

 # defaults (external interface)

@ -323,71 +351,71 @@ connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led]
 connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo]
 connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic]

-# hdmi peripherals
+# hdmi

-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
+connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk] 
+
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
+
+connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
+
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] 
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk] 
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk] 
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] 
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] 
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] 
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] 
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk] 
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] 
-connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk] 

-connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m09 [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m10 [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
-
-connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]

-connect_bd_net -net sys_concat_intc_intr_06 [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut]
+connect_bd_net -net axi_hdmi_tx_core_hdmi_clk      [get_bd_pins axi_hdmi_core/hdmi_clk]              [get_bd_pins axi_hdmi_clkgen/clk_0]           
+connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk  [get_bd_pins axi_hdmi_core/hdmi_out_clk]          [get_bd_ports hdmi_out_clk]                   
+connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync    [get_bd_pins axi_hdmi_core/hdmi_16_hsync]         [get_bd_ports hdmi_hsync]                     
+connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync    [get_bd_pins axi_hdmi_core/hdmi_16_vsync]         [get_bd_ports hdmi_vsync]                     
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e   [get_bd_pins axi_hdmi_core/hdmi_16_data_e]        [get_bd_ports hdmi_data_e]                    
+connect_bd_net -net axi_hdmi_tx_core_hdmi_data     [get_bd_pins axi_hdmi_core/hdmi_16_data]          [get_bd_ports hdmi_data]                      
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]  
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]  
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast    [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]     [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]  
+connect_bd_net -net axi_hdmi_tx_core_mm2s_tready   [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]    [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]     [get_bd_pins axi_hdmi_dma/mm2s_fsync]         
+connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync    [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]

-connect_bd_net -net axi_hdmi_core_hdmi_out_clk  [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk]
-connect_bd_net -net axi_hdmi_core_hdmi_hsync    [get_bd_ports hdmi_hsync]   [get_bd_pins axi_hdmi_core/hdmi_16_hsync]
-connect_bd_net -net axi_hdmi_core_hdmi_vsync    [get_bd_ports hdmi_vsync]   [get_bd_pins axi_hdmi_core/hdmi_16_vsync]
-connect_bd_net -net axi_hdmi_core_hdmi_data_e   [get_bd_ports hdmi_data_e]  [get_bd_pins axi_hdmi_core/hdmi_16_data_e]
-connect_bd_net -net axi_hdmi_core_hdmi_data     [get_bd_ports hdmi_data]    [get_bd_pins axi_hdmi_core/hdmi_16_data]
-
-connect_bd_net -net axi_hdmi_clkgen_clk [get_bd_pins axi_hdmi_clkgen/clk_0]           [get_bd_pins axi_hdmi_core/hdmi_clk]
-connect_bd_net -net axi_hdmi_core_valid [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]
-connect_bd_net -net axi_hdmi_core_data  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]
-connect_bd_net -net axi_hdmi_core_keep  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]
-connect_bd_net -net axi_hdmi_core_last  [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]  [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]
-connect_bd_net -net axi_hdmi_core_ready [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]
-connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_dma/mm2s_fsync]         [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]
-connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
+connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut]

 # spdif audio

+connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
+connect_bd_intf_net -intf_net axi_cpu_interconnect_m05_axi [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] 
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] 
+connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] 
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source
+connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] 
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] 
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] 

-connect_bd_intf_net -intf_net axi_cpu_interconnect_m11 [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
-connect_bd_intf_net -intf_net axi_cpu_interconnect_m12 [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
-connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
-
-connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
-connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
+connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
+connect_bd_intf_net -intf_net axi_mem_interconnect_s04_axi [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source
 connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
@ -398,36 +426,41 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_data  [get_bd_pins axi_spdif_tx_core/S
 connect_bd_net -net axi_spdif_tx_dma_mm2s_last  [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST]  [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast]
 connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]

-connect_bd_net -net sys_concat_intc_intr_07 [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
+connect_bd_net -net sys_concat_aux_intc_intr_07 [get_bd_pins sys_concat_aux_intc/In6] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]

 connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
 connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
 connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]

-# address mapping
+# address map

-create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem]          SEG_data_dlmb_cntlr
-create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs sys_mb_debug/S_AXI/Reg]           SEG_data_mb_debug
-create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]     SEG_data_ddr_cntrl
-create_bd_addr_seg -range 0x00002000 -offset 0x40E00000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_ethernet/s_axi/Reg]           SEG_data_ethernetlite
-create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg]           SEG_data_gpio_lcd
-create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg]        SEG_data_gpio_sw_led
-create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_intc/s_axi/Reg]               SEG_data_intc
-create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_timer/s_axi/Reg]              SEG_data_timer
-create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_uart/s_axi/Reg]               SEG_data_uart
+set sys_zynq 0
+set sys_mem_size 0x40000000 
+set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]

-create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_iic_main/s_axi/Reg]           SEG_data_iic
-create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]   SEG_data_hdmi_clkgen
-create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]      SEG_data_hdmi_dma
-create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]     SEG_data_hdmi_core
-create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]     SEG_data_spdif_tx_core
-create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces sys_mb/Data]  [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg]  SEG_data_spdif_tx_dma
+create_bd_addr_seg -range 0x00002000 -offset 0x00000000 $sys_addr_cntrl_space [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem]          SEG_data_dlmb_cntlr
+create_bd_addr_seg -range 0x00001000 -offset 0x41400000 $sys_addr_cntrl_space [get_bd_addr_segs sys_mb_debug/S_AXI/Reg]           SEG_data_mb_debug
+create_bd_addr_seg -range 0x40000000 -offset 0x80000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]     SEG_data_ddr_cntrl
+create_bd_addr_seg -range 0x00002000 -offset 0x40E00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ethernet/s_axi/Reg]           SEG_data_ethernetlite
+create_bd_addr_seg -range 0x00010000 -offset 0x40010000 $sys_addr_cntrl_space [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg]           SEG_data_gpio_lcd
+create_bd_addr_seg -range 0x00010000 -offset 0x40020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg]        SEG_data_gpio_sw_led
+create_bd_addr_seg -range 0x00010000 -offset 0x41200000 $sys_addr_cntrl_space [get_bd_addr_segs axi_intc/s_axi/Reg]               SEG_data_intc
+create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_timer/s_axi/Reg]              SEG_data_timer
+create_bd_addr_seg -range 0x00010000 -offset 0x40600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_uart/s_axi/Reg]               SEG_data_uart
+
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg]           SEG_data_iic_main
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]   SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]      SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]     SEG_data_hdmi_core
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]     SEG_data_spdif_core
+create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg]  SEG_data_spdif_tx_dma

 create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction]   [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem]        SEG_instr_ilmb_cntlr
 create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction]   [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]   SEG_instr_ddr_cntrl

-create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]   SEG_axi_ddr_cntrl
-create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG]   [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]   SEG_axi_ddr_cntrl
-create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]   SEG_axi_ddr_cntrl
+create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]   SEG_axi_ddr_cntrl
+create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG]   [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]   SEG_axi_ddr_cntrl
+create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr]   SEG_axi_ddr_cntrl
+


--- a/projects/common/zc702/zc702_system_bd.tcl
+++ b/projects/common/zc702/zc702_system_bd.tcl
@ -186,13 +186,15 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESET

 # address map

+set sys_zynq 1
 set sys_mem_size 0x40000000 
+set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]

-create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
-create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
-create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
-create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
-create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core

 create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm

--- a/projects/common/zc706/zc706_system_bd.tcl
+++ b/projects/common/zc706/zc706_system_bd.tcl
@ -186,13 +186,15 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESET

 # address map

+set sys_zynq 1
 set sys_mem_size 0x40000000 
+set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]

-create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
-create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
-create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
-create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
-create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core

 create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm

--- a/projects/common/zed/zed_system_bd.tcl
+++ b/projects/common/zed/zed_system_bd.tcl
@ -271,15 +271,17 @@ connect_bd_net -net sys_concat_intc_din_4 [get_bd_pins sys_concat_intc/In4] [get

 # address map

+set sys_zynq 1
 set sys_mem_size 0x20000000 
+set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]

-create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
-create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
-create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
-create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
-create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core
-create_bd_addr_seg -range 0x00010000 -offset 0x77600000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_i2s_adi/S_AXI/reg0]             SEG_data_i2s_adi
-create_bd_addr_seg -range 0x00010000 -offset 0x41620000 [get_bd_addr_spaces sys_ps7/Data]  [get_bd_addr_segs axi_iic_fmc/s_axi/Reg]              SEG_data_iic_fmc
+create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_iic_main/s_axi/Reg]             SEG_data_iic_main
+create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite]     SEG_data_hdmi_clkgen
+create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg]        SEG_data_hdmi_dma
+create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite]       SEG_data_hdmi_core
+create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0]       SEG_data_spdif_core
+create_bd_addr_seg -range 0x00010000 -offset 0x77600000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_i2s_adi/S_AXI/reg0]             SEG_data_i2s_adi
+create_bd_addr_seg -range 0x00010000 -offset 0x41620000 $sys_addr_cntrl_space  [get_bd_addr_segs axi_iic_fmc/s_axi/Reg]              SEG_data_iic_fmc

 create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S]     [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm

--- a/projects/fmcomms1/common/fmcomms1_bd.tcl
+++ b/projects/fmcomms1/common/fmcomms1_bd.tcl
@ -28,9 +28,11 @@ set ref_clk         [create_bd_port -dir O ref_clk]
 set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122]

 set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
+set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9122_dma
 set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
-set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {4}] $axi_ad9122_dma
+set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma
 set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
+set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9122_dma
 set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9122_dma

 set axi_ad9122_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9122_dma_interconnect]
@ -54,6 +56,10 @@ set_property -dict [list CONFIG.S_DATA_WIDTH {64}] $sys_ad9643_util_wfifo

 set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma]
 set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9643_dma
+set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma
+set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma
+set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma
+set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9643_dma
 set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9643_dma

 set axi_ad9643_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9643_dma_interconnect]
@ -184,15 +190,31 @@ connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/
 connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
 connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]

-# ila (adc)
+# ila (adc) - need a fifo, zed ila can not run at 250MHz
+
+set ila_adc_fifo  [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:11.0 ila_adc_fifo]
+set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $ila_adc_fifo
+set_property -dict [list CONFIG.Input_Data_Width {28}] $ila_adc_fifo
+set_property -dict [list CONFIG.Input_Depth {32}] $ila_adc_fifo
+set_property -dict [list CONFIG.Output_Data_Width {56}] $ila_adc_fifo
+set_property -dict [list CONFIG.Overflow_Flag {true}] $ila_adc_fifo
+set_property -dict [list CONFIG.Reset_Pin {false}] $ila_adc_fifo

 set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc]
 set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_adc
-set_property -dict [list CONFIG.C_PROBE0_WIDTH {28}] $ila_adc
+set_property -dict [list CONFIG.C_PROBE0_WIDTH {56}] $ila_adc
 set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc

-connect_bd_net -net adc_clk [get_bd_pins ila_adc/clk]
-connect_bd_net -net axi_ad9643_adc_mon_data   [get_bd_pins axi_ad9643/adc_mon_data]   [get_bd_pins ila_adc/probe0]
+set ila_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ila_constant_1]
+
+
+connect_bd_net -net axi_ad9643_adc_mon_data [get_bd_pins axi_ad9643/adc_mon_data] [get_bd_pins ila_adc_fifo/din]
+connect_bd_net -net adc_clk [get_bd_pins axi_ad9643/adc_clk] [get_bd_pins ila_adc_fifo/wr_clk]
+connect_bd_net -net sys_fmc_dma_clk  [get_bd_pins ila_adc_fifo/rd_clk]
+connect_bd_net -net xlconstant_0_const [get_bd_pins ila_adc_fifo/rd_en] [get_bd_pins ila_adc_fifo/wr_en] [get_bd_pins ila_constant_1/const]
+
+connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc/clk]
+connect_bd_net -net ila_adc_fifo_dout [get_bd_pins ila_adc_fifo/dout] [get_bd_pins ila_adc/probe0]

 # reference clock

--- a/projects/fmcomms1/zc702/system_constr.xdc
+++ b/projects/fmcomms1/zc702/system_constr.xdc
@ -82,10 +82,10 @@ set_property  -dict {PACKAGE_PIN N20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_p

 # clocks

-create_clock -name dac_clk_in   -period  2.10 [get_ports dac_clk_in_p]
-create_clock -name adc_clk_in   -period  4.06 [get_ports adc_clk_in_p]
+create_clock -name dac_clk_in   -period  2.16 [get_ports dac_clk_in_p]
+create_clock -name adc_clk_in   -period  4.00 [get_ports adc_clk_in_p]
 create_clock -name dac_div_clk  -period  8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
-create_clock -name adc_clk      -period  4.06 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
+create_clock -name adc_clk      -period  4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
 create_clock -name fmc_dma_clk  -period  8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]

 set_clock_groups -asynchronous -group {dac_div_clk}
--- a/projects/fmcomms1/zc706/system_constr.xdc
+++ b/projects/fmcomms1/zc706/system_constr.xdc
@ -86,7 +86,9 @@ create_clock -name dac_clk_in   -period  2.00 [get_ports dac_clk_in_p]
 create_clock -name adc_clk_in   -period  4.00 [get_ports adc_clk_in_p]
 create_clock -name dac_div_clk  -period  8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
 create_clock -name adc_clk      -period  4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
+create_clock -name fmc_dma_clk  -period  8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]

 set_clock_groups -asynchronous -group {dac_div_clk}
 set_clock_groups -asynchronous -group {adc_clk}
+set_clock_groups -asynchronous -group {fmc_dma_clk}

--- a/projects/fmcomms1/zed/system_constr.xdc
+++ b/projects/fmcomms1/zed/system_constr.xdc
@ -82,11 +82,12 @@ set_property  -dict {PACKAGE_PIN N20   IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_p

 # clocks

-create_clock -name dac_clk_in   -period  2.10 [get_ports dac_clk_in_p]
-create_clock -name adc_clk_in   -period  4.06 [get_ports adc_clk_in_p]
+create_clock -name dac_clk_in   -period  2.16 [get_ports dac_clk_in_p]
+create_clock -name adc_clk_in   -period  4.00 [get_ports adc_clk_in_p]
 create_clock -name dac_div_clk  -period  8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
-create_clock -name adc_clk      -period  4.06 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
+create_clock -name adc_clk      -period  4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
+create_clock -name fmc_dma_clk  -period  8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]

 set_clock_groups -asynchronous -group {dac_div_clk}
 set_clock_groups -asynchronous -group {adc_clk}
-
+set_clock_groups -asynchronous -group {fmc_dma_clk}