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axi_dmac: Make internal resets active high 

All the FPGA internal control signals are active high, using a active low
reset inserts a extra invert LUT. By using a active high reset we can avoid
that.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-04-17 17:00:13 +02:00
parent dc2b37bd0c
commit 9c249d25ab
2 changed files with 9 additions and 9 deletions
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2
library/axi_dmac/axi_dmac_constr.xdc
View File

@ -165,7 +165,7 @@ set_max_delay \
# Reset signals
set_false_path \
-from $req_clk \
-to [get_pins -hier *resetn_shift_reg*/CLR]
-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
# Not sure why, but it seems the built-in constraints for the RAM36B are wrong
set_max_delay \

16
library/axi_dmac/request_arb.v
View File

@ -339,28 +339,28 @@ end
// Generate reset for reset-less interfaces
generate if (C_DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI || C_DMA_TYPE_SRC == DMA_TYPE_FIFO) begin
reg [2:0] src_resetn_shift = 3'b0;
assign src_resetn = src_resetn_shift[2];
reg [2:0] src_reset_shift = 3'b0;
assign src_resetn = ~src_reset_shift[2];
always @(negedge req_aresetn or posedge src_clk) begin
if (~req_aresetn)
src_resetn_shift <= 3'b000;
src_reset_shift <= 3'b111;
else
src_resetn_shift <= {src_resetn_shift[1:0], 1'b1};
src_reset_shift <= {src_reset_shift[1:0], 1'b0};
end
end endgenerate
generate if (C_DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI || C_DMA_TYPE_DEST == DMA_TYPE_FIFO) begin
reg [2:0] dest_resetn_shift = 3'b0;
assign dest_resetn = dest_resetn_shift[2];
reg [2:0] dest_reset_shift = 3'b0;
assign dest_resetn = ~dest_reset_shift[2];
always @(negedge req_aresetn or posedge dest_clk) begin
if (~req_aresetn)
dest_resetn_shift <= 3'b000;
dest_reset_shift <= 3'b111;
else
dest_resetn_shift <= {dest_resetn_shift[1:0], 1'b1};
dest_reset_shift <= {dest_reset_shift[1:0], 1'b0};
end
end endgenerate