From 9c04491e1bb585196cc69330d3b68eb0e7f0f813 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 20 Feb 2015 15:09:09 +0100 Subject: [PATCH] fmcomms1: Add extra AXI slice on ADC DMA path Add a extra AXI slice on the ADC DMA data path to the HP interconnect to improve the timing. Signed-off-by: Lars-Peter Clausen --- projects/fmcomms1/zed/system_bd.tcl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/projects/fmcomms1/zed/system_bd.tcl b/projects/fmcomms1/zed/system_bd.tcl index 219ae0b2b..58b9dfc27 100644 --- a/projects/fmcomms1/zed/system_bd.tcl +++ b/projects/fmcomms1/zed/system_bd.tcl @@ -2,4 +2,12 @@ source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source ../common/fmcomms1_bd.tcl - + # Add extra register slice between ADC DMA and HP1 to meet timing + delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 + set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0] + connect_bd_intf_net [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] + connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI] + connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1] + connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] + assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }]