From 9b6531f79fc77052df8af66c752ac23abe4dc05a Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 17 Mar 2015 16:52:58 -0400 Subject: [PATCH] ad6676evb: 2014.4 updates --- projects/ad6676evb/zc706/system_top.v | 274 ++++++++++++++------------ 1 file changed, 149 insertions(+), 125 deletions(-) diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v index a7a1e04a8..eb048ebb6 100644 --- a/projects/ad6676evb/zc706/system_top.v +++ b/projects/ad6676evb/zc706/system_top.v @@ -41,28 +41,28 @@ module system_top ( - DDR_addr, - DDR_ba, - DDR_cas_n, - DDR_ck_n, - DDR_ck_p, - DDR_cke, - DDR_cs_n, - DDR_dm, - DDR_dq, - DDR_dqs_n, - DDR_dqs_p, - DDR_odt, - DDR_ras_n, - DDR_reset_n, - DDR_we_n, + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, - FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp, - FIXED_IO_mio, - FIXED_IO_ps_clk, - FIXED_IO_ps_porb, - FIXED_IO_ps_srstb, + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, gpio_bd, @@ -102,28 +102,28 @@ module system_top ( spi_mosi, spi_miso); - inout [14:0] DDR_addr; - inout [ 2:0] DDR_ba; - inout DDR_cas_n; - inout DDR_ck_n; - inout DDR_ck_p; - inout DDR_cke; - inout DDR_cs_n; - inout [ 3:0] DDR_dm; - inout [31:0] DDR_dq; - inout [ 3:0] DDR_dqs_n; - inout [ 3:0] DDR_dqs_p; - inout DDR_odt; - inout DDR_ras_n; - inout DDR_reset_n; - inout DDR_we_n; + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; - inout FIXED_IO_ddr_vrn; - inout FIXED_IO_ddr_vrp; - inout [53:0] FIXED_IO_mio; - inout FIXED_IO_ps_clk; - inout FIXED_IO_ps_porb; - inout FIXED_IO_ps_srstb; + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; inout [14:0] gpio_bd; @@ -165,14 +165,22 @@ module system_top ( // internal registers - reg dma_wr = 'd0; - reg [63:0] dma_data = 'd0; + reg adc_dwr = 'd0; + reg [63:0] adc_ddata = 'd0; // internal signals - wire [41:0] gpio_i; - wire [41:0] gpio_o; - wire [41:0] gpio_t; + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 2:0] spi0_csn; + wire spi0_clk; + wire spi0_mosi; + wire spi0_miso; + wire [ 2:0] spi1_csn; + wire spi1_clk; + wire spi1_mosi; + wire spi1_miso; wire rx_ref_clk; wire rx_sysref; wire rx_sync; @@ -181,39 +189,38 @@ module system_top ( wire [31:0] adc_data_a; wire adc_enable_b; wire [31:0] adc_data_b; - wire [15:0] ps_intrs; // pack & unpack here always @(posedge adc_clk) begin case ({adc_enable_b, adc_enable_a}) 2'b11: begin - dma_wr <= 1'b1; - dma_data[63:48] <= adc_data_b[31:16]; - dma_data[47:32] <= adc_data_a[31:16]; - dma_data[31:16] <= adc_data_b[15: 0]; - dma_data[15: 0] <= adc_data_a[15: 0]; + adc_dwr <= 1'b1; + adc_ddata[63:48] <= adc_data_b[31:16]; + adc_ddata[47:32] <= adc_data_a[31:16]; + adc_ddata[31:16] <= adc_data_b[15: 0]; + adc_ddata[15: 0] <= adc_data_a[15: 0]; end 2'b10: begin - dma_wr <= ~dma_wr; - dma_data[63:48] <= adc_data_b[31:16]; - dma_data[47:32] <= adc_data_b[15: 0]; - dma_data[31:16] <= dma_data[63:48]; - dma_data[15: 0] <= dma_data[47:32]; + adc_dwr <= ~adc_dwr; + adc_ddata[63:48] <= adc_data_b[31:16]; + adc_ddata[47:32] <= adc_data_b[15: 0]; + adc_ddata[31:16] <= adc_ddata[63:48]; + adc_ddata[15: 0] <= adc_ddata[47:32]; end 2'b01: begin - dma_wr <= ~dma_wr; - dma_data[63:48] <= adc_data_a[31:16]; - dma_data[47:32] <= adc_data_a[15: 0]; - dma_data[31:16] <= dma_data[63:48]; - dma_data[15: 0] <= dma_data[47:32]; + adc_dwr <= ~adc_dwr; + adc_ddata[63:48] <= adc_data_a[31:16]; + adc_ddata[47:32] <= adc_data_a[15: 0]; + adc_ddata[31:16] <= adc_ddata[63:48]; + adc_ddata[15: 0] <= adc_ddata[47:32]; end default: begin - dma_wr <= 1'b0; - dma_data[63:48] <= 16'd0; - dma_data[47:32] <= 16'd0; - dma_data[31:16] <= 16'd0; - dma_data[15: 0] <= 16'd0; + adc_dwr <= 1'b0; + adc_ddata[63:48] <= 16'd0; + adc_ddata[47:32] <= 16'd0; + adc_ddata[31:16] <= 16'd0; + adc_ddata[15: 0] <= 16'd0; end endcase end @@ -237,10 +244,15 @@ module system_top ( .O (rx_sync_p), .OB (rx_sync_n)); - ad_iobuf #(.DATA_WIDTH(25)) i_iobuf ( - .dt ({gpio_t[41:32], gpio_t[14:0]}), - .di ({gpio_o[41:32], gpio_o[14:0]}), - .do ({gpio_i[41:32], gpio_i[14:0]}), + assign spi_csn = spi0_csn[0]; + assign spi_clk = spi0_clk; + assign spi_mosi = spi0_mosi; + assign spi0_miso = spi_miso; + + ad_iobuf #(.DATA_WIDTH(10)) i_iobuf ( + .dt (gpio_t[41:32]), + .di (gpio_o[41:32]), + .do (gpio_i[41:32]), .dio ({ adc_oen, adc_sela, adc_selb, @@ -250,47 +262,49 @@ module system_top ( adc_agc1, adc_agc2, adc_agc3, - adc_agc4, - gpio_bd})); + adc_agc4})); + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dt (gpio_t[14:0]), + .di (gpio_o[14:0]), + .do (gpio_i[14:0]), + .dio (gpio_bd)); system_wrapper i_system_wrapper ( - .DDR_addr (DDR_addr), - .DDR_ba (DDR_ba), - .DDR_cas_n (DDR_cas_n), - .DDR_ck_n (DDR_ck_n), - .DDR_ck_p (DDR_ck_p), - .DDR_cke (DDR_cke), - .DDR_cs_n (DDR_cs_n), - .DDR_dm (DDR_dm), - .DDR_dq (DDR_dq), - .DDR_dqs_n (DDR_dqs_n), - .DDR_dqs_p (DDR_dqs_p), - .DDR_odt (DDR_odt), - .DDR_ras_n (DDR_ras_n), - .DDR_reset_n (DDR_reset_n), - .DDR_we_n (DDR_we_n), - .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), - .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), - .FIXED_IO_mio (FIXED_IO_mio), - .FIXED_IO_ps_clk (FIXED_IO_ps_clk), - .FIXED_IO_ps_porb (FIXED_IO_ps_porb), - .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), - .GPIO_I (gpio_i), - .GPIO_O (gpio_o), - .GPIO_T (gpio_t), - .ad6676_dma_intr (ps_intrs[13]), - .ad6676_gpio_intr (), - .ad6676_spi_intr (), .adc_clk (adc_clk), .adc_data_a (adc_data_a), .adc_data_b (adc_data_b), + .adc_ddata (adc_ddata), + .adc_dsync (1'b1), + .adc_dwr (adc_dwr), .adc_enable_a (adc_enable_a), .adc_enable_b (adc_enable_b), .adc_valid_a (), .adc_valid_b (), - .dma_data (dma_data), - .dma_sync (1'b1), - .dma_wr (dma_wr), + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -298,33 +312,43 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .ps_intr_0 (ps_intrs[0]), - .ps_intr_1 (ps_intrs[1]), - .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), - .ps_intr_2 (ps_intrs[2]), - .ps_intr_3 (ps_intrs[3]), - .ps_intr_4 (ps_intrs[4]), - .ps_intr_5 (ps_intrs[5]), - .ps_intr_6 (ps_intrs[6]), - .ps_intr_7 (ps_intrs[7]), - .ps_intr_8 (ps_intrs[8]), - .ps_intr_9 (ps_intrs[9]), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_12 (1'b0), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), .rx_sync (rx_sync), .rx_sysref (rx_sysref), .spdif (spdif), - .spi_clk_i (1'b0), - .spi_clk_o (spi_clk), - .spi_csn_i (1'b1), - .spi_csn_o (spi_csn), - .spi_sdi_i (spi_miso), - .spi_sdo_i (1'b0), - .spi_sdo_o (spi_mosi)); + .spi0_clk_i (spi0_clk), + .spi0_clk_o (spi0_clk), + .spi0_csn_0_o (spi0_csn[0]), + .spi0_csn_1_o (spi0_csn[1]), + .spi0_csn_2_o (spi0_csn[2]), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi0_miso), + .spi0_sdo_i (spi0_mosi), + .spi0_sdo_o (spi0_mosi), + .spi1_clk_i (spi1_clk), + .spi1_clk_o (spi1_clk), + .spi1_csn_0_o (spi1_csn[0]), + .spi1_csn_1_o (spi1_csn[1]), + .spi1_csn_2_o (spi1_csn[2]), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b1), + .spi1_sdo_i (spi1_mosi), + .spi1_sdo_o (spi1_mosi)); endmodule