From 9b425736ac4ca8ff5d9174dea1d8d8067560a1b5 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 20 May 2015 10:41:21 -0400 Subject: [PATCH] library: altera ip modifications --- library/axi_ad9144/axi_ad9144_hw.tcl | 46 ++++++++++--------- library/axi_ad9680/axi_ad9680_hw.tcl | 34 +++++++------- library/util_cpack/util_cpack_hw.tcl | 66 ++++++++++++++++++---------- 3 files changed, 80 insertions(+), 66 deletions(-) diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl index 0f561c66b..23a975b87 100755 --- a/library/axi_ad9144/axi_ad9144_hw.tcl +++ b/library/axi_ad9144/axi_ad9144_hw.tcl @@ -2,6 +2,7 @@ package require -exact qsys 13.0 source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl set_module_property NAME axi_ad9144 set_module_property DESCRIPTION "AXI AD9144 Interface" @@ -81,32 +82,29 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface -add_interface xcvr_clk clock end -add_interface_port xcvr_clk tx_clk clk Input 1 +add_interface if_tx_clk clock end +add_interface_port if_tx_clk tx_clk clk Input 1 -add_interface xcvr_data conduit end -set_interface_property xcvr_data associatedClock xcvr_clk -add_interface_port xcvr_data tx_data data Output 128*(PCORE_QUAD_DUAL_N+1) +add_interface if_tx_data avalon_streaming start +set_interface_property if_tx_data associatedClock if_tx_clk +set_interface_property if_tx_data dataBitsPerSymbol 128*(PCORE_QUAD_DUAL_N+1) +add_interface_port if_tx_data tx_data data Output 128*(PCORE_QUAD_DUAL_N+1) # dma interface -add_interface dac_clock clock start -add_interface_port dac_clock dac_clk clk Output 1 - -add_interface dac_dma_if conduit start -set_interface_property dac_dma_if associatedClock dac_clock -add_interface_port dac_dma_if dac_valid_0 dac_valid_0 Output 1 -add_interface_port dac_dma_if dac_enable_0 dac_enable_0 Output 1 -add_interface_port dac_dma_if dac_data_0 dac_data_0 Input 64 -add_interface_port dac_dma_if dac_valid_1 dac_valid_1 Output 1 -add_interface_port dac_dma_if dac_enable_1 dac_enable_1 Output 1 -add_interface_port dac_dma_if dac_data_1 dac_data_1 Input 64 -add_interface_port dac_dma_if dac_valid_2 dac_valid_2 Output 1 -add_interface_port dac_dma_if dac_enable_2 dac_enable_2 Output 1 -add_interface_port dac_dma_if dac_data_2 dac_data_2 Input 64 -add_interface_port dac_dma_if dac_valid_3 dac_valid_3 Output 1 -add_interface_port dac_dma_if dac_enable_3 dac_enable_3 Output 1 -add_interface_port dac_dma_if dac_data_3 dac_data_3 Input 64 -add_interface_port dac_dma_if dac_dovf dac_dovf Input 1 -add_interface_port dac_dma_if dac_dunf dac_dunf Input 1 +ad_alt_intf clock dac_clk output 1 +ad_alt_intf signal dac_valid_0 output 1 +ad_alt_intf signal dac_enable_0 output 1 +ad_alt_intf signal dac_data_0 input 64 +ad_alt_intf signal dac_valid_1 output 1 +ad_alt_intf signal dac_enable_1 output 1 +ad_alt_intf signal dac_data_1 input 64 +ad_alt_intf signal dac_valid_2 output 1 +ad_alt_intf signal dac_enable_2 output 1 +ad_alt_intf signal dac_data_2 input 64 +ad_alt_intf signal dac_valid_3 output 1 +ad_alt_intf signal dac_enable_3 output 1 +ad_alt_intf signal dac_data_3 input 64 +ad_alt_intf signal dac_dovf input 1 +ad_alt_intf signal dac_dunf input 1 diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl index c35c5662d..e5924fd44 100755 --- a/library/axi_ad9680/axi_ad9680_hw.tcl +++ b/library/axi_ad9680/axi_ad9680_hw.tcl @@ -2,6 +2,7 @@ package require -exact qsys 13.0 source ../scripts/adi_env.tcl +source ../scripts/adi_ip_alt.tcl set_module_property NAME axi_ad9680 set_module_property DESCRIPTION "AXI AD9680 Interface" @@ -71,26 +72,23 @@ add_interface_port s_axi s_axi_rready rready Input 1 # transceiver interface -add_interface xcvr_clk clock end -add_interface_port xcvr_clk rx_clk clk Input 1 +add_interface if_rx_clk clock end +add_interface_port if_rx_clk rx_clk clk Input 1 -add_interface xcvr_data conduit end -set_interface_property xcvr_data associatedClock xcvr_clk -add_interface_port xcvr_data rx_data data Input 128 +add_interface if_rx_data avalon_streaming end +set_interface_property if_rx_data associatedClock if_rx_clk +set_interface_property if_rx_data dataBitsPerSymbol 128 +add_interface_port if_rx_data rx_data data Input 128 # dma interface -add_interface adc_clock clock start -add_interface_port adc_clock adc_clk clk Output 1 - -add_interface adc_dma_if conduit start -set_interface_property adc_dma_if associatedClock adc_clock -add_interface_port adc_dma_if adc_valid_0 adc_valid_0 Output 1 -add_interface_port adc_dma_if adc_enable_0 adc_enable_0 Output 1 -add_interface_port adc_dma_if adc_data_0 adc_data_0 Input 64 -add_interface_port adc_dma_if adc_valid_1 adc_valid_1 Output 1 -add_interface_port adc_dma_if adc_enable_1 adc_enable_1 Output 1 -add_interface_port adc_dma_if adc_data_1 adc_data_1 Input 64 -add_interface_port adc_dma_if adc_dovf adc_dovf Input 1 -add_interface_port adc_dma_if adc_dunf adc_dunf Input 1 +ad_alt_intf clock adc_clock output 1 +ad_alt_intf signal adc_valid_0 output 1 +ad_alt_intf signal adc_enable_0 output 1 +ad_alt_intf signal adc_data_0 output 64 +ad_alt_intf signal adc_valid_1 output 1 +ad_alt_intf signal adc_enable_1 output 1 +ad_alt_intf signal adc_data_1 output 64 +ad_alt_intf signal adc_dovf input 1 +ad_alt_intf signal adc_dunf input 1 diff --git a/library/util_cpack/util_cpack_hw.tcl b/library/util_cpack/util_cpack_hw.tcl index 076d20902..571285ea1 100755 --- a/library/util_cpack/util_cpack_hw.tcl +++ b/library/util_cpack/util_cpack_hw.tcl @@ -9,6 +9,7 @@ set_module_property NAME util_cpack set_module_property DESCRIPTION "Channel Pack Utility" set_module_property VERSION 1.0 set_module_property DISPLAY_NAME util_cpack +set_module_property ELABORATION_CALLBACK p_util_cpack # files @@ -38,32 +39,49 @@ set_parameter_property CH_CNT HDL_PARAMETER true ad_alt_intf clock adc_clk input 1 ad_alt_intf signal adc_rst input 1 -ad_alt_intf signal adc_valid_0 input 1 -ad_alt_intf signal adc_enable_0 input 1 -ad_alt_intf signal adc_data_0 input CH_DW -ad_alt_intf signal adc_valid_1 input 1 -ad_alt_intf signal adc_enable_1 input 1 -ad_alt_intf signal adc_data_1 input CH_DW -ad_alt_intf signal adc_valid_2 input 1 -ad_alt_intf signal adc_enable_2 input 1 -ad_alt_intf signal adc_data_2 input CH_DW -ad_alt_intf signal adc_valid_3 input 1 -ad_alt_intf signal adc_enable_3 input 1 -ad_alt_intf signal adc_data_3 input CH_DW -ad_alt_intf signal adc_valid_4 input 1 -ad_alt_intf signal adc_enable_4 input 1 -ad_alt_intf signal adc_data_4 input CH_DW -ad_alt_intf signal adc_valid_5 input 1 -ad_alt_intf signal adc_enable_5 input 1 -ad_alt_intf signal adc_data_5 input CH_DW -ad_alt_intf signal adc_valid_6 input 1 -ad_alt_intf signal adc_enable_6 input 1 -ad_alt_intf signal adc_data_6 input CH_DW -ad_alt_intf signal adc_valid_7 input 1 -ad_alt_intf signal adc_enable_7 input 1 -ad_alt_intf signal adc_data_7 input CH_DW ad_alt_intf signal adc_valid output 1 ad_alt_intf signal adc_sync output 1 ad_alt_intf signal adc_data output CH_CNT*CH_DW +ad_alt_intf signal adc_valid_0 input 1 +ad_alt_intf signal adc_enable_0 input 1 +ad_alt_intf signal adc_data_0 input CH_DW +proc p_util_cpack {} { + + if {[get_parameter_value CH_CNT] > 1} { + ad_alt_intf signal adc_valid_1 input 1 + ad_alt_intf signal adc_enable_1 input 1 + ad_alt_intf signal adc_data_1 input CH_DW + } + if {[get_parameter_value CH_CNT] > 2} { + ad_alt_intf signal adc_valid_2 input 1 + ad_alt_intf signal adc_enable_2 input 1 + ad_alt_intf signal adc_data_2 input CH_DW + } + if {[get_parameter_value CH_CNT] > 3} { + ad_alt_intf signal adc_valid_3 input 1 + ad_alt_intf signal adc_enable_3 input 1 + ad_alt_intf signal adc_data_3 input CH_DW + } + if {[get_parameter_value CH_CNT] > 4} { + ad_alt_intf signal adc_valid_4 input 1 + ad_alt_intf signal adc_enable_4 input 1 + ad_alt_intf signal adc_data_4 input CH_DW + } + if {[get_parameter_value CH_CNT] > 5} { + ad_alt_intf signal adc_valid_5 input 1 + ad_alt_intf signal adc_enable_5 input 1 + ad_alt_intf signal adc_data_5 input CH_DW + } + if {[get_parameter_value CH_CNT] > 6} { + ad_alt_intf signal adc_valid_6 input 1 + ad_alt_intf signal adc_enable_6 input 1 + ad_alt_intf signal adc_data_6 input CH_DW + } + if {[get_parameter_value CH_CNT] > 7} { + ad_alt_intf signal adc_valid_7 input 1 + ad_alt_intf signal adc_enable_7 input 1 + ad_alt_intf signal adc_data_7 input CH_DW + } +}