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daq2: update adcfifo/dacfifo

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Laszlo Nagy 2019-01-22 13:19:37 +00:00 committed by Laszlo Nagy
parent b98eb28dca
commit 9b048f1a0e
9 changed files with 18 additions and 36 deletions
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3
projects/daq2/a10gx/system_qsys.tcl
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@ -1,8 +1,5 @@
set dac_fifo_name avl_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source $ad_hdl_dir/projects/common/altera/dacfifo_qsys.tcl

3
projects/daq2/a10soc/system_qsys.tcl
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@ -1,8 +1,5 @@
set dac_fifo_name avl_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl

12
projects/daq2/common/daq2_bd.tcl
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@ -1,6 +1,14 @@
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_fifo_name axi_ad9680_fifo
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_data_width 128
set dac_dma_data_width 128
# dac peripherals
ad_ip_instance axi_adxcvr axi_ad9144_xcvr
@ -31,6 +39,8 @@ ad_ip_parameter axi_ad9144_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_ad9144_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
# adc peripherals
ad_ip_instance axi_adxcvr axi_ad9680_xcvr
@ -61,6 +71,8 @@ ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
# shared transceiver core
ad_ip_instance util_adxcvr util_daq2_xcvr

6
projects/daq2/common/daq2_qsys.tcl
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@ -1,4 +1,8 @@
set dac_fifo_name avl_ad9144_fifo
set dac_data_width 128
set dac_dma_data_width 128
# ad9144-xcvr
add_instance ad9144_jesd204 adi_jesd204
@ -45,6 +49,8 @@ add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1
# dac fifo
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
add_interface tx_fifo_bypass conduit end
set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9144_fifo.if_bypass

6
projects/daq2/kc705/system_bd.tcl
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@ -1,15 +1,9 @@
## FIFO depth is 4Mb - 250k samples
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
## FIFO depth is 4Mb - 250k samples
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 15
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~80%

6
projects/daq2/kcu105/system_bd.tcl
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@ -1,15 +1,9 @@
## FIFO depth is 4Mb - 250k samples
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
## FIFO depth is 4Mb - 250k samples
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 15
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~70%

6
projects/daq2/vc707/system_bd.tcl
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@ -1,15 +1,9 @@
## FIFO depth is 8Mb - 500k samples
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 17
set adc_data_width 128
set adc_dma_data_width 64
## FIFO depth is 8Mb - 500k samples
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~68.45%

6
projects/daq2/zc706/system_bd.tcl
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@ -1,15 +1,9 @@
## FIFO depth is 1GB, PL_DDR is used
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
## FIFO depth is 8Mb - 500k samples
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~51%

6
projects/daq2/zcu102/system_bd.tcl
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@ -1,15 +1,9 @@
## FIFO depth is 8Mb - 500k samples
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 17
set adc_data_width 128
set adc_dma_data_width 64
## FIFO depth is 8Mb - 500k samples
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%