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fmcadc4: Convert to ADI JESD204 

Convert the FMCADC4 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-05-05 18:52:26 +02:00
parent bbe457acea
commit 9a917ae8bf
2 changed files with 14 additions and 7 deletions
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14
projects/fmcadc4/common/fmcadc4_bd.tcl
View File

@ -1,4 +1,6 @@
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# fmcadc4
# adc peripherals
@ -13,9 +15,7 @@ ad_ip_parameter axi_ad9680_xcvr CONFIG.NUM_OF_LANES 8
ad_ip_parameter axi_ad9680_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9680_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_instance jesd204 axi_ad9680_jesd
ad_ip_parameter axi_ad9680_jesd CONFIG.C_NODE_IS_TRANSMIT 0
ad_ip_parameter axi_ad9680_jesd CONFIG.C_LANES 8
adi_axi_jesd204_rx_create axi_ad9680_jesd 8
ad_ip_instance axi_dmac axi_ad9680_dma
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 1
@ -59,9 +59,9 @@ ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_0/rx_clk
ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_1/rx_clk
ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_0/rx_sof
ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_1/rx_sof
ad_connect axi_ad9680_jesd/rx_tdata util_bsplit_rx_data/data
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_0/rx_sof
ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_core_1/rx_sof
ad_connect axi_ad9680_jesd/rx_data_tdata util_bsplit_rx_data/data
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst
# connections (adc)
@ -101,7 +101,7 @@ ad_connect sys_cpu_resetn util_fmcadc4_xcvr/up_rstn
ad_cpu_interconnect 0x44A60000 axi_ad9680_xcvr
ad_cpu_interconnect 0x44A00000 axi_ad9680_core_0
ad_cpu_interconnect 0x44A10000 axi_ad9680_core_1
ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4

7
projects/fmcadc4/zc706/Makefile
View File

@ -19,13 +19,16 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
M_DEPS += ../../common/zc706/zc706_plddr3_adcfifo_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
@ -63,7 +66,9 @@ clean-all:clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/jesd204/axi_jesd204_rx clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/jesd204/jesd204_rx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
@ -81,7 +86,9 @@ lib:
make -C ../../../library/axi_clkgen
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/jesd204/axi_jesd204_rx
make -C ../../../library/axi_spdif_tx
make -C ../../../library/jesd204/jesd204_rx
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack