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util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate 

Left new parameters values in binary, as that's the way they are generated with the wizard, so future diff should be easier
main
Adrian Costina 2018-07-06 13:04:53 +01:00
parent 563710e904
commit 9a74a40c49
2 changed files with 28 additions and 25 deletions
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34
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -1594,9 +1594,9 @@ module util_adxcvr_xch #(
.CLK_COR_SEQ_2_ENABLE (4'b1111), .CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"), .CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1'h1), .CLK_COR_SEQ_LEN (1'h1),
.CPLL_CFG0 (16'h01fa), .CPLL_CFG0 (16'b0000001111111110),
.CPLL_CFG1 (16'h0023), .CPLL_CFG1 (16'b0000000000100001),
.CPLL_CFG2 (16'h0002), .CPLL_CFG2 (16'b0000001000000011),
.CPLL_CFG3 (16'h0000), .CPLL_CFG3 (16'h0000),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (5), .CPLL_FBDIV_45 (5),
@ -1692,7 +1692,7 @@ module util_adxcvr_xch #(
.PD_TRANS_TIME_FROM_P2 (12'h03c), .PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h19), .PD_TRANS_TIME_NONE_P2 (8'h19),
.PD_TRANS_TIME_TO_P2 (8'h64), .PD_TRANS_TIME_TO_P2 (8'h64),
.PREIQ_FREQ_BST (1'h0), .PREIQ_FREQ_BST (1),
.PROCESS_PAR (3'b010), .PROCESS_PAR (3'b010),
.RATE_SW_USE_DRP (1'b1), .RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0), .RCLK_SIPO_DLY_ENB (1'b0),
@ -1714,16 +1714,18 @@ module util_adxcvr_xch #(
.RXBUF_THRESH_UNDFLW (3), .RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001), .RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001), .RXCDRPHRESET_TIME (5'b00001),
.RXCDR_CFG0 (16'h0002), .RXCDR_CFG0 (16'b0000000000000011),
.RXCDR_CFG0_GEN3 (16'h0003), .RXCDR_CFG0_GEN3 (16'h0003),
.RXCDR_CFG1 (16'h0000), .RXCDR_CFG1 (16'h0000),
.RXCDR_CFG1_GEN3 (16'h0000), .RXCDR_CFG1_GEN3 (16'h0000),
.RXCDR_CFG2 (16'h0265), .RXCDR_CFG2 (16'h0265),
.RXCDR_CFG2_GEN2 (16'h0265),
.RXCDR_CFG2_GEN3 (16'h0265), .RXCDR_CFG2_GEN3 (16'h0265),
.RXCDR_CFG2_GEN4 (16'h00b4), .RXCDR_CFG2_GEN4 (16'b0000000101100100),
.RXCDR_CFG3 (16'h0012), .RXCDR_CFG3 (16'b0000000000011010),
.RXCDR_CFG3_GEN3 (16'h0012), .RXCDR_CFG3_GEN2 (6'b011010),
.RXCDR_CFG3_GEN4 (16'h0024), .RXCDR_CFG3_GEN3 (16'b0000000000011010),
.RXCDR_CFG3_GEN4 (16'b0000000000010010),
.RXCDR_CFG4 (16'h5cf6), .RXCDR_CFG4 (16'h5cf6),
.RXCDR_CFG4_GEN3 (16'h5cf6), .RXCDR_CFG4_GEN3 (16'h5cf6),
.RXCDR_CFG5 (16'hb46b), .RXCDR_CFG5 (16'hb46b),
@ -1751,7 +1753,7 @@ module util_adxcvr_xch #(
.RXDFELPM_KL_CFG1 (16'ha0e2), .RXDFELPM_KL_CFG1 (16'ha0e2),
.RXDFELPM_KL_CFG2 (16'h0100), .RXDFELPM_KL_CFG2 (16'h0100),
.RXDFE_CFG0 (16'h0a00), .RXDFE_CFG0 (16'h0a00),
.RXDFE_CFG1 (16'h0280), .RXDFE_CFG1 (16'b0000000000000000),
.RXDFE_GC_CFG0 (16'h0000), .RXDFE_GC_CFG0 (16'h0000),
.RXDFE_GC_CFG1 (16'h8000), .RXDFE_GC_CFG1 (16'h8000),
.RXDFE_GC_CFG2 (16'hffe0), .RXDFE_GC_CFG2 (16'hffe0),
@ -1818,8 +1820,8 @@ module util_adxcvr_xch #(
.RXPHSLIP_CFG (16'h9933), .RXPHSLIP_CFG (16'h9933),
.RXPH_MONITOR_SEL (5'b00000), .RXPH_MONITOR_SEL (5'b00000),
.RXPI_AUTO_BW_SEL_BYPASS (1'b0), .RXPI_AUTO_BW_SEL_BYPASS (1'b0),
.RXPI_CFG0 (16'h0002), .RXPI_CFG0 (16'b0010000000000100),
.RXPI_CFG1 (16'b0000000000010101), .RXPI_CFG1 (16'b0000000000000000),
.RXPI_LPM (1'b0), .RXPI_LPM (1'b0),
.RXPI_SEL_LC (2'b00), .RXPI_SEL_LC (2'b00),
.RXPI_STARTCODE (2'b00), .RXPI_STARTCODE (2'b00),
@ -1889,7 +1891,7 @@ module util_adxcvr_xch #(
.RX_TUNE_AFE_OS (2'b00), .RX_TUNE_AFE_OS (2'b00),
.RX_VREG_CTRL (3'b101), .RX_VREG_CTRL (3'b101),
.RX_VREG_PDB (1'b1), .RX_VREG_PDB (1'b1),
.RX_WIDEMODE_CDR (2'b00), .RX_WIDEMODE_CDR (2'b01),
.RX_WIDEMODE_CDR_GEN3 (2'b00), .RX_WIDEMODE_CDR_GEN3 (2'b00),
.RX_WIDEMODE_CDR_GEN4 (2'b01), .RX_WIDEMODE_CDR_GEN4 (2'b01),
.RX_XCLK_SEL ("RXDES"), .RX_XCLK_SEL ("RXDES"),
@ -1928,11 +1930,11 @@ module util_adxcvr_xch #(
.TXPH_CFG (16'h0323), .TXPH_CFG (16'h0323),
.TXPH_CFG2 (16'h0000), .TXPH_CFG2 (16'h0000),
.TXPH_MONITOR_SEL (5'b00000), .TXPH_MONITOR_SEL (5'b00000),
.TXPI_CFG (16'h0054), .TXPI_CFG (16'b0000000000000000),
.TXPI_CFG0 (2'b00), .TXPI_CFG0 (2'b00),
.TXPI_CFG1 (2'b00), .TXPI_CFG1 (2'b00),
.TXPI_CFG2 (2'b00), .TXPI_CFG2 (2'b00),
.TXPI_CFG3 (1'b0), .TXPI_CFG3 (1'b1),
.TXPI_CFG4 (1'b0), .TXPI_CFG4 (1'b0),
.TXPI_CFG5 (3'b000), .TXPI_CFG5 (3'b000),
.TXPI_GRAY_SEL (1'b0), .TXPI_GRAY_SEL (1'b0),
@ -1980,7 +1982,7 @@ module util_adxcvr_xch #(
.TX_PHICAL_CFG0 (16'h0000), .TX_PHICAL_CFG0 (16'h0000),
.TX_PHICAL_CFG1 (16'h7e00), .TX_PHICAL_CFG1 (16'h7e00),
.TX_PHICAL_CFG2 (16'h0201), .TX_PHICAL_CFG2 (16'h0201),
.TX_PI_BIASSET (1'h1), .TX_PI_BIASSET (2'h2),
.TX_PI_IBIAS_MID (2'b00), .TX_PI_IBIAS_MID (2'b00),
.TX_PMADATA_OPT (1'b0), .TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0), .TX_PMA_POWER_SAVE (1'b0),

19
library/xilinx/util_adxcvr/util_adxcvr_xcm.v
View File

@ -353,26 +353,26 @@ module util_adxcvr_xcm #(
.BIAS_CFG_RSVD (16'h0000), .BIAS_CFG_RSVD (16'h0000),
.COMMON_CFG0 (16'h0000), .COMMON_CFG0 (16'h0000),
.COMMON_CFG1 (16'h0000), .COMMON_CFG1 (16'h0000),
.POR_CFG (16'h0006), .POR_CFG (16'b0000000000000000),
.PPF0_CFG (16'h0600), .PPF0_CFG (16'b0000100000000000),
.PPF1_CFG (16'h0600), .PPF1_CFG (16'h0600),
.QPLL0CLKOUT_RATE ("HALF"), .QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (16'h331c), .QPLL0_CFG0 (16'h331c),
.QPLL0_CFG1 (16'hd038), .QPLL0_CFG1 (16'b1101000000111000),
.QPLL0_CFG1_G3 (16'hd038), .QPLL0_CFG1_G3 (16'b1101000000111000),
.QPLL0_CFG2 (16'h0fc0), .QPLL0_CFG2 (16'h0fc0),
.QPLL0_CFG2_G3 (16'h0fc0), .QPLL0_CFG2_G3 (16'b0000111111000001),
.QPLL0_CFG3 (16'h0120), .QPLL0_CFG3 (16'h0120),
.QPLL0_CFG4 (16'h0003), .QPLL0_CFG4 (16'b0000000000000100),
.QPLL0_CP (10'b0001111111), .QPLL0_CP (10'b0011111111),
.QPLL0_CP_G3 (10'b0000011111), .QPLL0_CP_G3 (10'b0000001111),
.QPLL0_FBDIV (QPLL_FBDIV), .QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (160), .QPLL0_FBDIV_G3 (160),
.QPLL0_INIT_CFG0 (16'h02b2), .QPLL0_INIT_CFG0 (16'h02b2),
.QPLL0_INIT_CFG1 (8'h00), .QPLL0_INIT_CFG1 (8'h00),
.QPLL0_LOCK_CFG (16'h25e8), .QPLL0_LOCK_CFG (16'h25e8),
.QPLL0_LOCK_CFG_G3 (16'h25e8), .QPLL0_LOCK_CFG_G3 (16'h25e8),
.QPLL0_LPF (10'b0100110111), .QPLL0_LPF (10'b1101111111),
.QPLL0_LPF_G3 (10'b0111010101), .QPLL0_LPF_G3 (10'b0111010101),
.QPLL0_PCI_EN (1'b0), .QPLL0_PCI_EN (1'b0),
.QPLL0_RATE_SW_USE_DRP (1'b1), .QPLL0_RATE_SW_USE_DRP (1'b1),
@ -416,6 +416,7 @@ module util_adxcvr_xcm #(
.SDM0INITSEED0_1 (9'b000010001), .SDM0INITSEED0_1 (9'b000010001),
.SDM1INITSEED0_0 (16'b0000000100010001), .SDM1INITSEED0_0 (16'b0000000100010001),
.SDM1INITSEED0_1 (9'b000010001), .SDM1INITSEED0_1 (9'b000010001),
.SIM_DEVICE ("ULTRASCALE_PLUS"),
.SIM_MODE ("FAST"), .SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE")) .SIM_RESET_SPEEDUP ("TRUE"))
i_gthe4_common ( i_gthe4_common (