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moved fmcomms5

main
Rejeesh Kutty 2014-05-19 13:49:49 -04:00
parent 3aed3ba71c
commit 9a36075324
9 changed files with 1465 additions and 0 deletions
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373
projects/fmcomms5/common/fmcomms5_bd.tcl Normal file
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# fmcomms5
# master
set rx_clk_in_0_p [create_bd_port -dir I rx_clk_in_0_p]
set rx_clk_in_0_n [create_bd_port -dir I rx_clk_in_0_n]
set rx_frame_in_0_p [create_bd_port -dir I rx_frame_in_0_p]
set rx_frame_in_0_n [create_bd_port -dir I rx_frame_in_0_n]
set rx_data_in_0_p [create_bd_port -dir I -from 5 -to 0 rx_data_in_0_p]
set rx_data_in_0_n [create_bd_port -dir I -from 5 -to 0 rx_data_in_0_n]
set tx_clk_out_0_p [create_bd_port -dir O tx_clk_out_0_p]
set tx_clk_out_0_n [create_bd_port -dir O tx_clk_out_0_n]
set tx_frame_out_0_p [create_bd_port -dir O tx_frame_out_0_p]
set tx_frame_out_0_n [create_bd_port -dir O tx_frame_out_0_n]
set tx_data_out_0_p [create_bd_port -dir O -from 5 -to 0 tx_data_out_0_p]
set tx_data_out_0_n [create_bd_port -dir O -from 5 -to 0 tx_data_out_0_n]
# slave
set rx_clk_in_1_p [create_bd_port -dir I rx_clk_in_1_p]
set rx_clk_in_1_n [create_bd_port -dir I rx_clk_in_1_n]
set rx_frame_in_1_p [create_bd_port -dir I rx_frame_in_1_p]
set rx_frame_in_1_n [create_bd_port -dir I rx_frame_in_1_n]
set rx_data_in_1_p [create_bd_port -dir I -from 5 -to 0 rx_data_in_1_p]
set rx_data_in_1_n [create_bd_port -dir I -from 5 -to 0 rx_data_in_1_n]
set tx_clk_out_1_p [create_bd_port -dir O tx_clk_out_1_p]
set tx_clk_out_1_n [create_bd_port -dir O tx_clk_out_1_n]
set tx_frame_out_1_p [create_bd_port -dir O tx_frame_out_1_p]
set tx_frame_out_1_n [create_bd_port -dir O tx_frame_out_1_n]
set tx_data_out_1_p [create_bd_port -dir O -from 5 -to 0 tx_data_out_1_p]
set tx_data_out_1_n [create_bd_port -dir O -from 5 -to 0 tx_data_out_1_n]
# dma multiplexing
set ad9361_0_dac_ddata [create_bd_port -dir I -from 63 -to 0 ad9361_0_dac_ddata]
set ad9361_1_dac_ddata [create_bd_port -dir I -from 63 -to 0 ad9361_1_dac_ddata]
set ad9361_dac_ddata [create_bd_port -dir O -from 127 -to 0 ad9361_dac_ddata]
set ad9361_0_adc_ddata [create_bd_port -dir O -from 63 -to 0 ad9361_0_adc_ddata]
set ad9361_1_adc_ddata [create_bd_port -dir O -from 63 -to 0 ad9361_1_adc_ddata]
set ad9361_adc_ddata [create_bd_port -dir I -from 127 -to 0 ad9361_adc_ddata]
set sys_100m_resetn [create_bd_port -dir O sys_100m_resetn]
set sys_100m_clk [create_bd_port -dir O sys_100m_clk]
if {$sys_zynq == 0} {
set gpio_i [create_bd_port -dir I -from 32 -to 0 gpio_i]
set gpio_o [create_bd_port -dir O -from 32 -to 0 gpio_o]
set gpio_t [create_bd_port -dir O -from 32 -to 0 gpio_t]
}
if {$sys_zynq == 1} {
set spi_csn_0_i [create_bd_port -dir I spi_csn_0_i]
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_2_o [create_bd_port -dir O spi_csn_2_o]
} else {
set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o]
}
set spi_sclk_i [create_bd_port -dir I spi_sclk_i]
set spi_sclk_o [create_bd_port -dir O spi_sclk_o]
set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
set spi_miso_i [create_bd_port -dir I spi_miso_i]
# instances
set axi_ad9361_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_0]
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361_0
set_property -dict [list CONFIG.PCORE_IODELAY_GROUP {dev_0_if_delay_group}] $axi_ad9361_0
set axi_ad9361_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_1]
set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9361_1
set_property -dict [list CONFIG.PCORE_IODELAY_GROUP {dev_1_if_delay_group}] $axi_ad9361_1
set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_dac_dma
if {$sys_zynq == 1} {
set axi_ad9361_dac_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_dac_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_dac_dma_interconnect
}
set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
if {$sys_zynq == 1} {
set axi_ad9361_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_adc_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_adc_dma_interconnect
}
if {$sys_zynq == 0} {
set axi_fmcomms2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcomms2_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcomms2_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcomms2_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcomms2_spi
}
if {$sys_zynq == 0} {
set axi_fmcomms2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_fmcomms2_gpio]
set_property -dict [list CONFIG.C_IS_DUAL {0}] $axi_fmcomms2_gpio
set_property -dict [list CONFIG.C_GPIO_WIDTH {17}] $axi_fmcomms2_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcomms2_gpio
}
# additions to default configuration
if {$sys_zynq == 0} {
set_property -dict [list CONFIG.NUM_MI {12}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_PORTS {9}] $sys_concat_intc
} else {
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_PORTS {6}] $sys_concat_intc
}
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {64}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property LEFT 63 [get_bd_ports GPIO_I]
set_property LEFT 63 [get_bd_ports GPIO_O]
set_property LEFT 63 [get_bd_ports GPIO_T]
}
# connections (spi)
if {$sys_zynq == 0} {
connect_bd_net -net spi_csn_i [get_bd_pins axi_fmcomms2_spi/ss_i] [get_bd_ports spi_csn_i]
connect_bd_net -net spi_csn_o [get_bd_pins axi_fmcomms2_spi/ss_o] [get_bd_ports spi_csn_o]
connect_bd_net -net spi_sclk_i [get_bd_pins axi_fmcomms2_spi/sck_i] [get_bd_ports spi_sclk_i]
connect_bd_net -net spi_sclk_o [get_bd_pins axi_fmcomms2_spi/sck_o] [get_bd_ports spi_sclk_o]
connect_bd_net -net spi_mosi_i [get_bd_pins axi_fmcomms2_spi/io0_i] [get_bd_ports spi_mosi_i]
connect_bd_net -net spi_mosi_o [get_bd_pins axi_fmcomms2_spi/io0_o] [get_bd_ports spi_mosi_o]
connect_bd_net -net spi_miso_i [get_bd_pins axi_fmcomms2_spi/io1_i] [get_bd_ports spi_miso_i]
connect_bd_net -net spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In7]
} else {
connect_bd_net -net spi_csn_0_i [get_bd_pins sys_ps7/SPI0_SS_I] [get_bd_ports spi_csn_0_i]
connect_bd_net -net spi_csn_0_o [get_bd_pins sys_ps7/SPI0_SS_O] [get_bd_ports spi_csn_0_o]
connect_bd_net -net spi_csn_1_o [get_bd_pins sys_ps7/SPI0_SS1_O] [get_bd_ports spi_csn_1_o]
connect_bd_net -net spi_csn_2_o [get_bd_pins sys_ps7/SPI0_SS2_O] [get_bd_ports spi_csn_2_o]
connect_bd_net -net spi_sclk_i [get_bd_pins sys_ps7/SPI0_SCLK_I] [get_bd_ports spi_sclk_i]
connect_bd_net -net spi_sclk_o [get_bd_pins sys_ps7/SPI0_SCLK_O] [get_bd_ports spi_sclk_o]
connect_bd_net -net spi_mosi_i [get_bd_pins sys_ps7/SPI0_MOSI_I] [get_bd_ports spi_mosi_i]
connect_bd_net -net spi_mosi_o [get_bd_pins sys_ps7/SPI0_MOSI_O] [get_bd_ports spi_mosi_o]
connect_bd_net -net spi_miso_i [get_bd_pins sys_ps7/SPI0_MISO_I] [get_bd_ports spi_miso_i]
}
# connections (gpio)
if {$sys_zynq == 0} {
connect_bd_net -net gpio_i [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] [get_bd_ports gpio_i]
connect_bd_net -net gpio_o [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] [get_bd_ports gpio_o]
connect_bd_net -net gpio_t [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] [get_bd_ports gpio_t]
connect_bd_net -net gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In8]
}
# connections (ad9361)
connect_bd_net -net sys_100m_resetn [get_bd_ports sys_100m_resetn]
connect_bd_net -net sys_100m_clk [get_bd_ports sys_100m_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_0/delay_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_1/delay_clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_0/l_clk]
connect_bd_net -net axi_ad9361_1_clk [get_bd_pins axi_ad9361_1/l_clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_0/clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_1/clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_adc_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_dac_dma/fifo_rd_clk]
connect_bd_net -net axi_ad9361_0_dac_enable [get_bd_pins axi_ad9361_0/dac_enable_out]
connect_bd_net -net axi_ad9361_0_dac_enable [get_bd_pins axi_ad9361_0/dac_enable_in]
connect_bd_net -net axi_ad9361_0_dac_enable [get_bd_pins axi_ad9361_1/dac_enable_in]
connect_bd_net -net axi_ad9361_0_rx_clk_in_p [get_bd_ports rx_clk_in_0_p] [get_bd_pins axi_ad9361_0/rx_clk_in_p]
connect_bd_net -net axi_ad9361_0_rx_clk_in_n [get_bd_ports rx_clk_in_0_n] [get_bd_pins axi_ad9361_0/rx_clk_in_n]
connect_bd_net -net axi_ad9361_0_rx_frame_in_p [get_bd_ports rx_frame_in_0_p] [get_bd_pins axi_ad9361_0/rx_frame_in_p]
connect_bd_net -net axi_ad9361_0_rx_frame_in_n [get_bd_ports rx_frame_in_0_n] [get_bd_pins axi_ad9361_0/rx_frame_in_n]
connect_bd_net -net axi_ad9361_0_rx_data_in_p [get_bd_ports rx_data_in_0_p] [get_bd_pins axi_ad9361_0/rx_data_in_p]
connect_bd_net -net axi_ad9361_0_rx_data_in_n [get_bd_ports rx_data_in_0_n] [get_bd_pins axi_ad9361_0/rx_data_in_n]
connect_bd_net -net axi_ad9361_0_tx_clk_out_p [get_bd_ports tx_clk_out_0_p] [get_bd_pins axi_ad9361_0/tx_clk_out_p]
connect_bd_net -net axi_ad9361_0_tx_clk_out_n [get_bd_ports tx_clk_out_0_n] [get_bd_pins axi_ad9361_0/tx_clk_out_n]
connect_bd_net -net axi_ad9361_0_tx_frame_out_p [get_bd_ports tx_frame_out_0_p] [get_bd_pins axi_ad9361_0/tx_frame_out_p]
connect_bd_net -net axi_ad9361_0_tx_frame_out_n [get_bd_ports tx_frame_out_0_n] [get_bd_pins axi_ad9361_0/tx_frame_out_n]
connect_bd_net -net axi_ad9361_0_tx_data_out_p [get_bd_ports tx_data_out_0_p] [get_bd_pins axi_ad9361_0/tx_data_out_p]
connect_bd_net -net axi_ad9361_0_tx_data_out_n [get_bd_ports tx_data_out_0_n] [get_bd_pins axi_ad9361_0/tx_data_out_n]
connect_bd_net -net axi_ad9361_1_rx_clk_in_p [get_bd_ports rx_clk_in_1_p] [get_bd_pins axi_ad9361_1/rx_clk_in_p]
connect_bd_net -net axi_ad9361_1_rx_clk_in_n [get_bd_ports rx_clk_in_1_n] [get_bd_pins axi_ad9361_1/rx_clk_in_n]
connect_bd_net -net axi_ad9361_1_rx_frame_in_p [get_bd_ports rx_frame_in_1_p] [get_bd_pins axi_ad9361_1/rx_frame_in_p]
connect_bd_net -net axi_ad9361_1_rx_frame_in_n [get_bd_ports rx_frame_in_1_n] [get_bd_pins axi_ad9361_1/rx_frame_in_n]
connect_bd_net -net axi_ad9361_1_rx_data_in_p [get_bd_ports rx_data_in_1_p] [get_bd_pins axi_ad9361_1/rx_data_in_p]
connect_bd_net -net axi_ad9361_1_rx_data_in_n [get_bd_ports rx_data_in_1_n] [get_bd_pins axi_ad9361_1/rx_data_in_n]
connect_bd_net -net axi_ad9361_1_tx_clk_out_p [get_bd_ports tx_clk_out_1_p] [get_bd_pins axi_ad9361_1/tx_clk_out_p]
connect_bd_net -net axi_ad9361_1_tx_clk_out_n [get_bd_ports tx_clk_out_1_n] [get_bd_pins axi_ad9361_1/tx_clk_out_n]
connect_bd_net -net axi_ad9361_1_tx_frame_out_p [get_bd_ports tx_frame_out_1_p] [get_bd_pins axi_ad9361_1/tx_frame_out_p]
connect_bd_net -net axi_ad9361_1_tx_frame_out_n [get_bd_ports tx_frame_out_1_n] [get_bd_pins axi_ad9361_1/tx_frame_out_n]
connect_bd_net -net axi_ad9361_1_tx_data_out_p [get_bd_ports tx_data_out_1_p] [get_bd_pins axi_ad9361_1/tx_data_out_p]
connect_bd_net -net axi_ad9361_1_tx_data_out_n [get_bd_ports tx_data_out_1_n] [get_bd_pins axi_ad9361_1/tx_data_out_n]
connect_bd_net -net axi_ad9361_0_adc_dwr [get_bd_pins axi_ad9361_0/adc_dwr] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en]
connect_bd_net -net axi_ad9361_0_adc_dsync [get_bd_pins axi_ad9361_0/adc_dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9361_0_adc_ddata [get_bd_pins axi_ad9361_0/adc_ddata] [get_bd_ports ad9361_0_adc_ddata]
connect_bd_net -net axi_ad9361_1_adc_ddata [get_bd_pins axi_ad9361_1/adc_ddata] [get_bd_ports ad9361_1_adc_ddata]
connect_bd_net -net axi_ad9361_adc_ddata [get_bd_ports ad9361_adc_ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]
connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins axi_ad9361_0/dac_drd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en]
connect_bd_net -net axi_ad9361_0_dac_ddata [get_bd_pins axi_ad9361_0/dac_ddata] [get_bd_ports ad9361_0_dac_ddata]
connect_bd_net -net axi_ad9361_1_dac_ddata [get_bd_pins axi_ad9361_1/dac_ddata] [get_bd_ports ad9361_1_dac_ddata]
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_ports ad9361_dac_ddata] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In3]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9361_0/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9361_1/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_0/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_adc_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_dac_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9361_1/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_0/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_1/s_axi_aresetn]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_fmcomms2_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcomms2_gpio/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcomms2_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcomms2_spi/ext_spi_clk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcomms2_gpio/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcomms2_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcomms2_gpio/s_axi_aresetn]
}
# memory interconnects share the same clock (fclk2)
if {$sys_zynq == 1} {
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
}
# interconnect (mem/dac)
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/m_src_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn]
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_ad9361_dac_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9361_dac_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/m_src_axi]
connect_bd_intf_net -intf_net axi_ad9361_dac_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9361_dac_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aclk]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn]
connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn]
}
# ila (adc) master
set ila_adc_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_0]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {62}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {112}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE2_WIDTH {112}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE4_WIDTH {128}] $ila_adc_0
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins ila_adc_0/clk]
connect_bd_net -net axi_ad9361_0_dev_l_dbg_data [get_bd_pins axi_ad9361_0/dev_l_dbg_data] [get_bd_pins ila_adc_0/probe0]
connect_bd_net -net axi_ad9361_0_dev_dbg_data [get_bd_pins axi_ad9361_0/dev_dbg_data] [get_bd_pins ila_adc_0/probe1]
connect_bd_net -net axi_ad9361_1_dev_dbg_data [get_bd_pins axi_ad9361_1/dev_dbg_data] [get_bd_pins ila_adc_0/probe2]
connect_bd_net -net axi_ad9361_0_adc_dwr [get_bd_pins ila_adc_0/probe3]
connect_bd_net -net axi_ad9361_adc_ddata [get_bd_pins ila_adc_0/probe4]
# ila (adc) slave
set ila_adc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_1]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_adc_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {62}] $ila_adc_1
connect_bd_net -net axi_ad9361_1_clk [get_bd_pins ila_adc_1/clk]
connect_bd_net -net axi_ad9361_1_dev_l_dbg_data [get_bd_pins axi_ad9361_1/dev_l_dbg_data] [get_bd_pins ila_adc_1/probe0]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x79020000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_0/s_axi/axi_lite] SEG_data_ad9361_0
create_bd_addr_seg -range 0x00010000 -offset 0x7C420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_dac_dma/s_axi/axi_lite] SEG_data_ad9361_0_dac_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7C400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_adc_dma/s_axi/axi_lite] SEG_data_ad9361_0_adc_dma
create_bd_addr_seg -range 0x00010000 -offset 0x79040000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9361_1/s_axi/axi_lite] SEG_data_ad9361_1
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcomms2_spi/axi_lite/Reg] SEG_data_fmcomms2_spi
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcomms2_gpio/S_AXI/Reg] SEG_data_fmcomms2_gpio
}
if {$sys_zynq == 0} {
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
}

4
projects/fmcomms5/zc702/system_bd.tcl Normal file
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@ -0,0 +1,4 @@
source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
source ../common/fmcomms5_bd.tcl

139
projects/fmcomms5/zc702/system_constr.xdc Normal file
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@ -0,0 +1,139 @@
# constraints
# ad9361 master
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC1_LPC_LA17_CC_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC1_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_p] ; ## G12 FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_n] ; ## G13 FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_p] ; ## D14 FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_n] ; ## D15 FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[0]] ; ## H22 FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[1]] ; ## H23 FMC1_LPC_LA19_N
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[2]] ; ## G21 FMC1_LPC_LA20_P
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[3]] ; ## G22 FMC1_LPC_LA20_N
set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[4]] ; ## H25 FMC1_LPC_LA21_P
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[5]] ; ## H26 FMC1_LPC_LA21_N
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[6]] ; ## G24 FMC1_LPC_LA22_P
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[7]] ; ## G25 FMC1_LPC_LA22_N
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[0]] ; ## D23 FMC1_LPC_LA23_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[1]] ; ## D24 FMC1_LPC_LA23_N
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[2]] ; ## H28 FMC1_LPC_LA24_P
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[3]] ; ## H29 FMC1_LPC_LA24_N
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_0] ; ## G27 FMC1_LPC_LA25_P
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports mcs_sync] ; ## C22 FMC1_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_enable_0] ; ## G18 FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_0] ; ## G19 FMC1_LPC_LA16_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_2_0] ; ## D27 FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_rfen] ; ## H31 FMC1_LPC_LA28_P
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_lock] ; ## H37 FMC1_LPC_LA32_P
# spi
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H35 FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G34 FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## G33 FMC1_LPC_LA31_P
# ad9361 slave
set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G6 FMC2_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G7 FMC2_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D8 FMC2_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D9 FMC2_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H7 FMC2_LPC_LA02_P
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H8 FMC2_LPC_LA02_N
set_property -dict {PACKAGE_PIN AA16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G9 FMC2_LPC_LA03_P
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC2_LPC_LA03_N
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC2_LPC_LA04_P
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC2_LPC_LA04_N
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC2_LPC_LA05_P
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC2_LPC_LA05_N
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC2_LPC_LA06_P
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC2_LPC_LA06_N
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC2_LPC_LA07_P
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC2_LPC_LA07_N
set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_p] ; ## G12 FMC2_LPC_LA08_P
set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_n] ; ## G13 FMC2_LPC_LA08_N
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_p] ; ## D14 FMC2_LPC_LA09_P
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_n] ; ## D15 FMC2_LPC_LA09_N
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC2_LPC_LA10_P
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC2_LPC_LA10_N
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC2_LPC_LA11_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC2_LPC_LA11_N
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC2_LPC_LA12_P
set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC2_LPC_LA12_N
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC2_LPC_LA13_P
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC2_LPC_LA13_N
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC2_LPC_LA14_P
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC2_LPC_LA14_N
set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC2_LPC_LA15_P
set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC2_LPC_LA15_N
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[0]] ; ## H22 FMC2_LPC_LA19_P
set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[1]] ; ## H23 FMC2_LPC_LA19_N
set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[2]] ; ## G21 FMC2_LPC_LA20_P
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[3]] ; ## G22 FMC2_LPC_LA20_N
set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[4]] ; ## H25 FMC2_LPC_LA21_P
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[5]] ; ## H26 FMC2_LPC_LA21_N
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[6]] ; ## G24 FMC2_LPC_LA22_P
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[7]] ; ## G25 FMC2_LPC_LA22_N
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[0]] ; ## D23 FMC2_LPC_LA23_P
set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[1]] ; ## D24 FMC2_LPC_LA23_N
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[2]] ; ## H28 FMC2_LPC_LA24_P
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[3]] ; ## H29 FMC2_LPC_LA24_N
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_1] ; ## G27 FMC2_LPC_LA25_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports gpio_enable_1] ; ## G18 FMC2_LPC_LA16_P
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_1] ; ## G19 FMC2_LPC_LA16_N
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS25} [get_ports gpio_debug_3_1] ; ## C26 FMC2_LPC_LA27_P
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS25} [get_ports gpio_debug_4_1] ; ## C27 FMC2_LPC_LA27_N
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_3_1] ; ## D26 FMC2_LPC_LA26_P
set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_4_1] ; ## D27 FMC2_LPC_LA26_N
# clocks
create_clock -name rx_0_clk -period 5.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 5.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {ad9361_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create fmcomms5_zc702
adi_project_files fmcomms5_zc702 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
adi_project_run fmcomms5_zc702

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_clk_in_0_p,
rx_clk_in_0_n,
rx_frame_in_0_p,
rx_frame_in_0_n,
rx_data_in_0_p,
rx_data_in_0_n,
tx_clk_out_0_p,
tx_clk_out_0_n,
tx_frame_out_0_p,
tx_frame_out_0_n,
tx_data_out_0_p,
tx_data_out_0_n,
gpio_status_0,
gpio_ctl_0,
gpio_en_agc_0,
mcs_sync,
gpio_resetb_0,
gpio_enable_0,
gpio_txnrx_0,
gpio_debug_1_0,
gpio_debug_2_0,
gpio_calsw_1_0,
gpio_calsw_2_0,
gpio_ad5355_rfen,
gpio_ad5355_lock,
rx_clk_in_1_p,
rx_clk_in_1_n,
rx_frame_in_1_p,
rx_frame_in_1_n,
rx_data_in_1_p,
rx_data_in_1_n,
tx_clk_out_1_p,
tx_clk_out_1_n,
tx_frame_out_1_p,
tx_frame_out_1_n,
tx_data_out_1_p,
tx_data_out_1_n,
gpio_status_1,
gpio_ctl_1,
gpio_en_agc_1,
gpio_enable_1,
gpio_txnrx_1,
gpio_debug_3_1,
gpio_debug_4_1,
gpio_calsw_3_1,
gpio_calsw_4_1,
spi_ad9361_0,
spi_ad9361_1,
spi_ad5355,
spi_clk,
spi_mosi,
spi_miso,
ref_clk_p,
ref_clk_n);
inout [ 14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [ 31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [ 53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [ 15:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [ 15:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_clk_in_0_p;
input rx_clk_in_0_n;
input rx_frame_in_0_p;
input rx_frame_in_0_n;
input [ 5:0] rx_data_in_0_p;
input [ 5:0] rx_data_in_0_n;
output tx_clk_out_0_p;
output tx_clk_out_0_n;
output tx_frame_out_0_p;
output tx_frame_out_0_n;
output [ 5:0] tx_data_out_0_p;
output [ 5:0] tx_data_out_0_n;
inout [ 7:0] gpio_status_0;
inout [ 3:0] gpio_ctl_0;
inout gpio_en_agc_0;
output mcs_sync;
inout gpio_resetb_0;
inout gpio_enable_0;
inout gpio_txnrx_0;
inout gpio_debug_1_0;
inout gpio_debug_2_0;
inout gpio_calsw_1_0;
inout gpio_calsw_2_0;
inout gpio_ad5355_rfen;
inout gpio_ad5355_lock;
input rx_clk_in_1_p;
input rx_clk_in_1_n;
input rx_frame_in_1_p;
input rx_frame_in_1_n;
input [ 5:0] rx_data_in_1_p;
input [ 5:0] rx_data_in_1_n;
output tx_clk_out_1_p;
output tx_clk_out_1_n;
output tx_frame_out_1_p;
output tx_frame_out_1_n;
output [ 5:0] tx_data_out_1_p;
output [ 5:0] tx_data_out_1_n;
inout [ 7:0] gpio_status_1;
inout [ 3:0] gpio_ctl_1;
inout gpio_en_agc_1;
inout gpio_enable_1;
inout gpio_txnrx_1;
inout gpio_debug_3_1;
inout gpio_debug_4_1;
inout gpio_calsw_3_1;
inout gpio_calsw_4_1;
output spi_ad9361_0;
output spi_ad9361_1;
output spi_ad5355;
output spi_clk;
output spi_mosi;
input spi_miso;
input ref_clk_p;
input ref_clk_n;
// internal registers
reg [ 2:0] mcs_sync_m = 'd0;
reg mcs_sync = 'd0;
// internal signals
wire sys_100m_resetn;
wire sys_100m_clk;
wire ref_clk_s;
wire ref_clk;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 63:0] gpio_t;
wire gpio_open_45_45;
wire gpio_open_44_44;
wire [ 63:0] ad9361_0_adc_ddata;
wire [ 63:0] ad9361_0_dac_ddata;
wire [ 63:0] ad9361_1_adc_ddata;
wire [ 63:0] ad9361_1_dac_ddata;
// multi-chip synchronization
always @(posedge ref_clk or negedge sys_100m_resetn) begin
if (sys_100m_resetn == 1'b0) begin
mcs_sync_m <= 3'd0;
mcs_sync <= 1'd0;
end else begin
mcs_sync_m <= {mcs_sync_m[1:0], gpio_o[45]};
mcs_sync <= mcs_sync_m[2] & ~mcs_sync_m[1];
end
end
// instantiations
IBUFGDS i_ref_clk_ibuf (
.I (ref_clk_p),
.IB (ref_clk_n),
.O (ref_clk_s));
BUFR #(.BUFR_DIVIDE("BYPASS")) i_ref_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (ref_clk_s),
.O (ref_clk));
ad_iobuf #(.DATA_WIDTH(59)) i_iobuf (
.dt (gpio_t[58:0]),
.di (gpio_o[58:0]),
.do (gpio_i[58:0]),
.dio ({ gpio_ad5355_lock, // 58
gpio_ad5355_rfen, // 57
gpio_calsw_4_1, // 56
gpio_calsw_3_1, // 55
gpio_calsw_2_0, // 54
gpio_calsw_1_0, // 53
gpio_txnrx_1, // 52
gpio_enable_1, // 51
gpio_en_agc_1, // 50
gpio_txnrx_0, // 49
gpio_enable_0, // 48
gpio_en_agc_0, // 47
gpio_resetb_0, // 46
gpio_open_45_45, // 45
gpio_open_44_44, // 44
gpio_debug_4_1, // 43
gpio_debug_3_1, // 42
gpio_debug_2_0, // 41
gpio_debug_1_0, // 40
gpio_ctl_1, // 36
gpio_ctl_0, // 32
gpio_status_1, // 24
gpio_status_0, // 16
gpio_bd})); // 0
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ad9361_0_adc_ddata (ad9361_0_adc_ddata),
.ad9361_0_dac_ddata (ad9361_0_dac_ddata),
.ad9361_1_adc_ddata (ad9361_1_adc_ddata),
.ad9361_1_dac_ddata (ad9361_1_dac_ddata),
.ad9361_adc_ddata ({ad9361_0_adc_ddata, ad9361_1_adc_ddata}),
.ad9361_dac_ddata ({ad9361_0_dac_ddata, ad9361_1_dac_ddata}),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n),
.rx_clk_in_1_p (rx_clk_in_1_p),
.rx_data_in_0_n (rx_data_in_0_n),
.rx_data_in_0_p (rx_data_in_0_p),
.rx_data_in_1_n (rx_data_in_1_n),
.rx_data_in_1_p (rx_data_in_1_p),
.rx_frame_in_0_n (rx_frame_in_0_n),
.rx_frame_in_0_p (rx_frame_in_0_p),
.rx_frame_in_1_n (rx_frame_in_1_n),
.rx_frame_in_1_p (rx_frame_in_1_p),
.spdif (spdif),
.spi_csn_0_i (1'b1),
.spi_csn_0_o (spi_ad9361_0),
.spi_csn_1_o (spi_ad9361_1),
.spi_csn_2_o (spi_ad5355),
.spi_miso_i (spi_miso),
.spi_mosi_i (1'b0),
.spi_mosi_o (spi_mosi),
.spi_sclk_i (1'b0),
.spi_sclk_o (spi_clk),
.sys_100m_clk (sys_100m_clk),
.sys_100m_resetn (sys_100m_resetn),
.tx_clk_out_0_n (tx_clk_out_0_n),
.tx_clk_out_0_p (tx_clk_out_0_p),
.tx_clk_out_1_n (tx_clk_out_1_n),
.tx_clk_out_1_p (tx_clk_out_1_p),
.tx_data_out_0_n (tx_data_out_0_n),
.tx_data_out_0_p (tx_data_out_0_p),
.tx_data_out_1_n (tx_data_out_1_n),
.tx_data_out_1_p (tx_data_out_1_p),
.tx_frame_out_0_n (tx_frame_out_0_n),
.tx_frame_out_0_p (tx_frame_out_0_p),
.tx_frame_out_1_n (tx_frame_out_1_n),
.tx_frame_out_1_p (tx_frame_out_1_p));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/fmcomms5_bd.tcl

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# constraints
# ad9361 master
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC_HPC_LA17_CC_P
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC_HPC_LA17_CC_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_p] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS_25} [get_ports tx_clk_out_0_n] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_p] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_frame_out_0_n] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[0]] ; ## H22 FMC_HPC_LA19_P
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[1]] ; ## H23 FMC_HPC_LA19_N
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[2]] ; ## G21 FMC_HPC_LA20_P
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[3]] ; ## G22 FMC_HPC_LA20_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[4]] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[5]] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[6]] ; ## G24 FMC_HPC_LA22_P
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports gpio_status_0[7]] ; ## G25 FMC_HPC_LA22_N
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[0]] ; ## D23 FMC_HPC_LA23_P
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[1]] ; ## D24 FMC_HPC_LA23_N
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[2]] ; ## H28 FMC_HPC_LA24_P
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_0[3]] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_0] ; ## G27 FMC_HPC_LA25_P
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports mcs_sync] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports gpio_resetb_0] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports gpio_enable_0] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_0] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_1_0] ; ## C26 FMC_HPC_LA27_P
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_2_0] ; ## C27 FMC_HPC_LA27_N
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_1_0] ; ## D26 FMC_HPC_LA26_P
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_2_0] ; ## D27 FMC_HPC_LA26_N
set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_rfen] ; ## H31 FMC_HPC_LA28_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports gpio_ad5355_lock] ; ## H37 FMC_HPC_LA32_P
# spi
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC_HPC_LA29_P
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC_HPC_LA29_N
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC_HPC_LA30_P
set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H35 FMC_HPC_LA30_N
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## G33 FMC_HPC_LA31_P
set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G34 FMC_HPC_LA31_N
# ad9361 slave
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D09 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_p] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports tx_clk_out_1_n] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_p] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_frame_out_1_n] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[0]] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[1]] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[2]] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[3]] ; ## G22 FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[4]] ; ## H25 FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[5]] ; ## H26 FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[6]] ; ## G24 FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports gpio_status_1[7]] ; ## G25 FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[0]] ; ## D23 FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[1]] ; ## D24 FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[2]] ; ## H28 FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl_1[3]] ; ## H29 FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc_1] ; ## G27 FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gpio_enable_1] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx_1] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports gpio_debug_3_1] ; ## C26 FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports gpio_debug_4_1] ; ## C27 FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_3_1] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports gpio_calsw_4_1] ; ## D27 FMC_LPC_LA26_N
# clocks
create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_0_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]
create_clock -name ad9361_1_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_1/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {ad9361_0_clk}
set_clock_groups -asynchronous -group {ad9361_1_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}

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projects/fmcomms5/zc706/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create fmcomms5_zc706
adi_project_files fmcomms5_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run fmcomms5_zc706

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projects/fmcomms5/zc706/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_clk_in_0_p,
rx_clk_in_0_n,
rx_frame_in_0_p,
rx_frame_in_0_n,
rx_data_in_0_p,
rx_data_in_0_n,
tx_clk_out_0_p,
tx_clk_out_0_n,
tx_frame_out_0_p,
tx_frame_out_0_n,
tx_data_out_0_p,
tx_data_out_0_n,
gpio_status_0,
gpio_ctl_0,
gpio_en_agc_0,
mcs_sync,
gpio_resetb_0,
gpio_enable_0,
gpio_txnrx_0,
gpio_debug_1_0,
gpio_debug_2_0,
gpio_calsw_1_0,
gpio_calsw_2_0,
gpio_ad5355_rfen,
gpio_ad5355_lock,
rx_clk_in_1_p,
rx_clk_in_1_n,
rx_frame_in_1_p,
rx_frame_in_1_n,
rx_data_in_1_p,
rx_data_in_1_n,
tx_clk_out_1_p,
tx_clk_out_1_n,
tx_frame_out_1_p,
tx_frame_out_1_n,
tx_data_out_1_p,
tx_data_out_1_n,
gpio_status_1,
gpio_ctl_1,
gpio_en_agc_1,
gpio_enable_1,
gpio_txnrx_1,
gpio_debug_3_1,
gpio_debug_4_1,
gpio_calsw_3_1,
gpio_calsw_4_1,
spi_ad9361_0,
spi_ad9361_1,
spi_ad5355,
spi_clk,
spi_mosi,
spi_miso,
ref_clk_p,
ref_clk_n);
inout [ 14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [ 31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [ 53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [ 14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [ 23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_clk_in_0_p;
input rx_clk_in_0_n;
input rx_frame_in_0_p;
input rx_frame_in_0_n;
input [ 5:0] rx_data_in_0_p;
input [ 5:0] rx_data_in_0_n;
output tx_clk_out_0_p;
output tx_clk_out_0_n;
output tx_frame_out_0_p;
output tx_frame_out_0_n;
output [ 5:0] tx_data_out_0_p;
output [ 5:0] tx_data_out_0_n;
inout [ 7:0] gpio_status_0;
inout [ 3:0] gpio_ctl_0;
inout gpio_en_agc_0;
output mcs_sync;
inout gpio_resetb_0;
inout gpio_enable_0;
inout gpio_txnrx_0;
inout gpio_debug_1_0;
inout gpio_debug_2_0;
inout gpio_calsw_1_0;
inout gpio_calsw_2_0;
inout gpio_ad5355_rfen;
inout gpio_ad5355_lock;
input rx_clk_in_1_p;
input rx_clk_in_1_n;
input rx_frame_in_1_p;
input rx_frame_in_1_n;
input [ 5:0] rx_data_in_1_p;
input [ 5:0] rx_data_in_1_n;
output tx_clk_out_1_p;
output tx_clk_out_1_n;
output tx_frame_out_1_p;
output tx_frame_out_1_n;
output [ 5:0] tx_data_out_1_p;
output [ 5:0] tx_data_out_1_n;
inout [ 7:0] gpio_status_1;
inout [ 3:0] gpio_ctl_1;
inout gpio_en_agc_1;
inout gpio_enable_1;
inout gpio_txnrx_1;
inout gpio_debug_3_1;
inout gpio_debug_4_1;
inout gpio_calsw_3_1;
inout gpio_calsw_4_1;
output spi_ad9361_0;
output spi_ad9361_1;
output spi_ad5355;
output spi_clk;
output spi_mosi;
input spi_miso;
input ref_clk_p;
input ref_clk_n;
// internal registers
reg [ 2:0] mcs_sync_m = 'd0;
reg mcs_sync = 'd0;
// internal signals
wire sys_100m_resetn;
wire sys_100m_clk;
wire ref_clk_s;
wire ref_clk;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 63:0] gpio_t;
wire gpio_open_45_45;
wire gpio_open_44_44;
wire gpio_open_15_15;
wire [ 63:0] ad9361_0_adc_ddata;
wire [ 63:0] ad9361_0_dac_ddata;
wire [ 63:0] ad9361_1_adc_ddata;
wire [ 63:0] ad9361_1_dac_ddata;
// multi-chip synchronization
always @(posedge ref_clk or negedge sys_100m_resetn) begin
if (sys_100m_resetn == 1'b0) begin
mcs_sync_m <= 3'd0;
mcs_sync <= 1'd0;
end else begin
mcs_sync_m <= {mcs_sync_m[1:0], gpio_o[45]};
mcs_sync <= mcs_sync_m[2] & ~mcs_sync_m[1];
end
end
// instantiations
IBUFGDS i_ref_clk_ibuf (
.I (ref_clk_p),
.IB (ref_clk_n),
.O (ref_clk_s));
BUFR #(.BUFR_DIVIDE("BYPASS")) i_ref_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (ref_clk_s),
.O (ref_clk));
ad_iobuf #(.DATA_WIDTH(59)) i_iobuf (
.dt (gpio_t[58:0]),
.di (gpio_o[58:0]),
.do (gpio_i[58:0]),
.dio ({ gpio_ad5355_lock, // 58
gpio_ad5355_rfen, // 57
gpio_calsw_4_1, // 56
gpio_calsw_3_1, // 55
gpio_calsw_2_0, // 54
gpio_calsw_1_0, // 53
gpio_txnrx_1, // 52
gpio_enable_1, // 51
gpio_en_agc_1, // 50
gpio_txnrx_0, // 49
gpio_enable_0, // 48
gpio_en_agc_0, // 47
gpio_resetb_0, // 46
gpio_open_45_45, // 45
gpio_open_44_44, // 44
gpio_debug_4_1, // 43
gpio_debug_3_1, // 42
gpio_debug_2_0, // 41
gpio_debug_1_0, // 40
gpio_ctl_1, // 36
gpio_ctl_0, // 32
gpio_status_1, // 24
gpio_status_0, // 16
gpio_open_15_15, // 15
gpio_bd})); // 0
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ad9361_0_adc_ddata (ad9361_0_adc_ddata),
.ad9361_0_dac_ddata (ad9361_0_dac_ddata),
.ad9361_1_adc_ddata (ad9361_1_adc_ddata),
.ad9361_1_dac_ddata (ad9361_1_dac_ddata),
.ad9361_adc_ddata ({ad9361_0_adc_ddata, ad9361_1_adc_ddata}),
.ad9361_dac_ddata ({ad9361_0_dac_ddata, ad9361_1_dac_ddata}),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n),
.rx_clk_in_1_p (rx_clk_in_1_p),
.rx_data_in_0_n (rx_data_in_0_n),
.rx_data_in_0_p (rx_data_in_0_p),
.rx_data_in_1_n (rx_data_in_1_n),
.rx_data_in_1_p (rx_data_in_1_p),
.rx_frame_in_0_n (rx_frame_in_0_n),
.rx_frame_in_0_p (rx_frame_in_0_p),
.rx_frame_in_1_n (rx_frame_in_1_n),
.rx_frame_in_1_p (rx_frame_in_1_p),
.spdif (spdif),
.spi_csn_0_i (1'b1),
.spi_csn_0_o (spi_ad9361_0),
.spi_csn_1_o (spi_ad9361_1),
.spi_csn_2_o (spi_ad5355),
.spi_miso_i (spi_miso),
.spi_mosi_i (1'b0),
.spi_mosi_o (spi_mosi),
.spi_sclk_i (1'b0),
.spi_sclk_o (spi_clk),
.sys_100m_clk (sys_100m_clk),
.sys_100m_resetn (sys_100m_resetn),
.tx_clk_out_0_n (tx_clk_out_0_n),
.tx_clk_out_0_p (tx_clk_out_0_p),
.tx_clk_out_1_n (tx_clk_out_1_n),
.tx_clk_out_1_p (tx_clk_out_1_p),
.tx_data_out_0_n (tx_data_out_0_n),
.tx_data_out_0_p (tx_data_out_0_p),
.tx_data_out_1_n (tx_data_out_1_n),
.tx_data_out_1_p (tx_data_out_1_p),
.tx_frame_out_0_n (tx_frame_out_0_n),
.tx_frame_out_0_p (tx_frame_out_0_p),
.tx_frame_out_1_n (tx_frame_out_1_n),
.tx_frame_out_1_p (tx_frame_out_1_p));
endmodule
// ***************************************************************************
// ***************************************************************************