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axi_ad9379: Initial commit

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Adrian Costina 2017-09-01 17:26:37 +03:00
parent cb2fd6af73
commit 9a32240cc5
10 changed files with 2082 additions and 0 deletions
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library/axi_ad9379/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dcfilter.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_xcvr_rx_if.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9379.v
M_DEPS += axi_ad9379_if.v
M_DEPS += axi_ad9379_ip.tcl
M_DEPS += axi_ad9379_rx.v
M_DEPS += axi_ad9379_rx_channel.v
M_DEPS += axi_ad9379_rx_os.v
M_DEPS += axi_ad9379_tx.v
M_DEPS += axi_ad9379_tx_channel.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_ad9379.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_ad9379.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_ad9379_ip.tcl >> axi_ad9379_ip.log 2>&1
####################################################################################
####################################################################################

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library/axi_ad9379/axi_ad9379.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9379 #(
parameter ID = 0,
parameter DAC_DATAPATH_DISABLE = 0,
parameter ADC_DATAPATH_DISABLE = 0) (
// receive
input adc_clk,
input adc_rx_valid,
input [ 3:0] adc_rx_sof,
input [ 63:0] adc_rx_data,
output adc_rx_ready,
input adc_os_clk,
input adc_rx_os_valid,
input [ 3:0] adc_rx_os_sof,
input [ 63:0] adc_rx_os_data,
output adc_rx_os_ready,
// transmit
input dac_clk,
output dac_tx_valid,
output [127:0] dac_tx_data,
input dac_tx_ready,
// master/slave
input dac_sync_in,
output dac_sync_out,
// dma interface
output adc_enable_i0,
output adc_valid_i0,
output [ 15:0] adc_data_i0,
output adc_enable_q0,
output adc_valid_q0,
output [ 15:0] adc_data_q0,
output adc_enable_i1,
output adc_valid_i1,
output [ 15:0] adc_data_i1,
output adc_enable_q1,
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
output adc_os_enable_i0,
output adc_os_valid_i0,
output [ 31:0] adc_os_data_i0,
output adc_os_enable_q0,
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
output dac_enable_i0,
output dac_valid_i0,
input [ 31:0] dac_data_i0,
output dac_enable_q0,
output dac_valid_q0,
input [ 31:0] dac_data_q0,
output dac_enable_i1,
output dac_valid_i1,
input [ 31:0] dac_data_i1,
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// internal registers
reg up_wack = 'd0;
reg up_rack = 'd0;
reg [ 31:0] up_rdata = 'd0;
// internal signals
wire up_clk;
wire up_rstn;
wire adc_rst;
wire adc_os_rst;
wire [ 63:0] adc_data_s;
wire adc_os_valid_s;
wire [ 63:0] adc_os_data_s;
wire dac_rst;
wire [127:0] dac_data_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire [ 2:0] up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s[0:2];
wire [ 2:0] up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// defaults
assign dac_tx_valid = 1'b1;
assign adc_rx_ready = 1'b1;
assign adc_rx_os_ready = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
end
end
// device interface
axi_ad9379_if i_if (
.adc_clk (adc_clk),
.adc_rx_sof (adc_rx_sof),
.adc_rx_data (adc_rx_data),
.adc_os_clk (adc_os_clk),
.adc_rx_os_sof (adc_rx_os_sof),
.adc_rx_os_data (adc_rx_os_data),
.adc_data (adc_data_s),
.adc_os_valid (adc_os_valid_s),
.adc_os_data (adc_os_data_s),
.dac_clk (dac_clk),
.dac_tx_data (dac_tx_data),
.dac_data (dac_data_s));
// receive
axi_ad9379_rx #(
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx (
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_data (adc_data_s),
.adc_enable_i0 (adc_enable_i0),
.adc_valid_i0 (adc_valid_i0),
.adc_data_i0 (adc_data_i0),
.adc_enable_q0 (adc_enable_q0),
.adc_valid_q0 (adc_valid_q0),
.adc_data_q0 (adc_data_q0),
.adc_enable_i1 (adc_enable_i1),
.adc_valid_i1 (adc_valid_i1),
.adc_data_i1 (adc_data_i1),
.adc_enable_q1 (adc_enable_q1),
.adc_valid_q1 (adc_valid_q1),
.adc_data_q1 (adc_data_q1),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// receive (o/s)
axi_ad9379_rx_os #(
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx_os (
.adc_os_rst (adc_os_rst),
.adc_os_clk (adc_os_clk),
.adc_os_valid (adc_os_valid_s),
.adc_os_data (adc_os_data_s),
.adc_os_enable_i0 (adc_os_enable_i0),
.adc_os_valid_i0 (adc_os_valid_i0),
.adc_os_data_i0 (adc_os_data_i0),
.adc_os_enable_q0 (adc_os_enable_q0),
.adc_os_valid_q0 (adc_os_valid_q0),
.adc_os_data_q0 (adc_os_data_q0),
.adc_os_dovf (adc_os_dovf),
.adc_os_dunf (adc_os_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// transmit
axi_ad9379_tx #(
.ID (ID),
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
i_tx (
.dac_rst (dac_rst),
.dac_clk (dac_clk),
.dac_data (dac_data_s),
.dac_sync_in (dac_sync_in),
.dac_sync_out (dac_sync_out),
.dac_enable_i0 (dac_enable_i0),
.dac_valid_i0 (dac_valid_i0),
.dac_data_i0 (dac_data_i0),
.dac_enable_q0 (dac_enable_q0),
.dac_valid_q0 (dac_valid_q0),
.dac_data_q0 (dac_data_q0),
.dac_enable_i1 (dac_enable_i1),
.dac_valid_i1 (dac_valid_i1),
.dac_data_i1 (dac_data_i1),
.dac_enable_q1 (dac_enable_q1),
.dac_valid_q1 (dac_valid_q1),
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9379/axi_ad9379_hw.tcl Normal file
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package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
set_module_property NAME axi_ad9379
set_module_property DESCRIPTION "AXI AD9379 Interface"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad9379
# files
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9379
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_mul.v
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_dcfilter.v
add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
add_fileset_file axi_ad9379_if.v VERILOG PATH axi_ad9379_if.v
add_fileset_file axi_ad9379_rx_channel.v VERILOG PATH axi_ad9379_rx_channel.v
add_fileset_file axi_ad9379_rx.v VERILOG PATH axi_ad9379_rx.v
add_fileset_file axi_ad9379_rx_os.v VERILOG PATH axi_ad9379_rx_os.v
add_fileset_file axi_ad9379_tx_channel.v VERILOG PATH axi_ad9379_tx_channel.v
add_fileset_file axi_ad9379_tx.v VERILOG PATH axi_ad9379_tx.v
add_fileset_file axi_ad9379.v VERILOG PATH axi_ad9379.v TOP_LEVEL_FILE
add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc
add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc
add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc
add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/altera/common/up_rst_constr.sdc
# parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME ID
set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter DAC_DATAPATH_DISABLE INTEGER 0
set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
set_parameter_property DAC_DATAPATH_DISABLE TYPE INTEGER
set_parameter_property DAC_DATAPATH_DISABLE UNITS None
set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
add_parameter ADC_DATAPATH_DISABLE INTEGER 0
set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
set_parameter_property ADC_DATAPATH_DISABLE TYPE INTEGER
set_parameter_property ADC_DATAPATH_DISABLE UNITS None
set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
# transceiver interface
ad_alt_intf clock adc_clk input 1
ad_alt_intf signal adc_rx_sof input 4 export
add_interface if_adc_rx_data avalon_streaming sink
add_interface_port if_adc_rx_data adc_rx_data data input 64
add_interface_port if_adc_rx_data adc_rx_valid valid input 1
add_interface_port if_adc_rx_data adc_rx_ready ready output 1
set_interface_property if_adc_rx_data associatedClock if_adc_clk
set_interface_property if_adc_rx_data dataBitsPerSymbol 64
ad_alt_intf clock adc_os_clk input 1
ad_alt_intf signal adc_rx_os_sof input 4 export
add_interface if_adc_rx_os_data avalon_streaming sink
add_interface_port if_adc_rx_os_data adc_rx_os_data data input 64
add_interface_port if_adc_rx_os_data adc_rx_os_valid valid input 1
add_interface_port if_adc_rx_os_data adc_rx_os_ready ready output 1
set_interface_property if_adc_rx_os_data associatedClock if_adc_os_clk
set_interface_property if_adc_rx_os_data dataBitsPerSymbol 64
ad_alt_intf clock dac_clk input 1
add_interface if_dac_tx_data avalon_streaming source
add_interface_port if_dac_tx_data dac_tx_data data output 128
add_interface_port if_dac_tx_data dac_tx_valid valid output 1
add_interface_port if_dac_tx_data dac_tx_ready ready input 1
set_interface_property if_dac_tx_data associatedClock if_dac_clk
set_interface_property if_dac_tx_data dataBitsPerSymbol 128
# master/slave
ad_alt_intf signal dac_sync_in input 1
ad_alt_intf signal dac_sync_out output 1
# adc-channel interface
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_i0 enable Output 1
add_interface_port adc_ch_0 adc_valid_i0 valid Output 1
add_interface_port adc_ch_0 adc_data_i0 data Output 16
set_interface_property adc_ch_0 associatedClock if_adc_clk
set_interface_property adc_ch_0 associatedReset none
add_interface adc_ch_1 conduit end
add_interface_port adc_ch_1 adc_enable_q0 enable Output 1
add_interface_port adc_ch_1 adc_valid_q0 valid Output 1
add_interface_port adc_ch_1 adc_data_q0 data Output 16
set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset none
add_interface adc_ch_2 conduit end
add_interface_port adc_ch_2 adc_enable_i1 enable Output 1
add_interface_port adc_ch_2 adc_valid_i1 valid Output 1
add_interface_port adc_ch_2 adc_data_i1 data Output 16
set_interface_property adc_ch_2 associatedClock if_adc_clk
set_interface_property adc_ch_2 associatedReset none
add_interface adc_ch_3 conduit end
add_interface_port adc_ch_3 adc_enable_q1 enable Output 1
add_interface_port adc_ch_3 adc_valid_q1 valid Output 1
add_interface_port adc_ch_3 adc_data_q1 data Output 16
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf
# adc-os-channel interface
add_interface adc_os_ch_0 conduit end
add_interface_port adc_os_ch_0 adc_os_enable_i0 enable Output 1
add_interface_port adc_os_ch_0 adc_os_valid_i0 valid Output 1
add_interface_port adc_os_ch_0 adc_os_data_i0 data Output 32
set_interface_property adc_os_ch_0 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_0 associatedReset none
add_interface adc_os_ch_1 conduit end
add_interface_port adc_os_ch_1 adc_os_enable_q0 enable Output 1
add_interface_port adc_os_ch_1 adc_os_valid_q0 valid Output 1
add_interface_port adc_os_ch_1 adc_os_data_q0 data Output 32
set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_1 associatedReset none
ad_alt_intf signal adc_os_dovf input 1 ovf
ad_alt_intf signal adc_os_dunf input 1 unf
# dac-channel interface
add_interface dac_ch_0 conduit end
add_interface_port dac_ch_0 dac_enable_i0 enable Output 1
add_interface_port dac_ch_0 dac_valid_i0 valid Output 1
add_interface_port dac_ch_0 dac_data_i0 data Input 32
set_interface_property dac_ch_0 associatedClock if_dac_clk
set_interface_property dac_ch_0 associatedReset none
add_interface dac_ch_1 conduit end
add_interface_port dac_ch_1 dac_enable_q0 enable Output 1
add_interface_port dac_ch_1 dac_valid_q0 valid Output 1
add_interface_port dac_ch_1 dac_data_q0 data Input 32
set_interface_property dac_ch_1 associatedClock if_dac_clk
set_interface_property dac_ch_1 associatedReset none
add_interface dac_ch_2 conduit end
add_interface_port dac_ch_2 dac_enable_i1 enable Output 1
add_interface_port dac_ch_2 dac_valid_i1 valid Output 1
add_interface_port dac_ch_2 dac_data_i1 data Input 32
set_interface_property dac_ch_2 associatedClock if_dac_clk
set_interface_property dac_ch_2 associatedReset none
add_interface dac_ch_3 conduit end
add_interface_port dac_ch_3 dac_enable_q1 enable Output 1
add_interface_port dac_ch_3 dac_valid_q1 valid Output 1
add_interface_port dac_ch_3 dac_data_q1 data Input 32
set_interface_property dac_ch_3 associatedClock if_dac_clk
set_interface_property dac_ch_3 associatedReset none
ad_alt_intf signal dac_dovf input 1 ovf
ad_alt_intf signal dac_dunf input 1 unf

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9379_if (
// receive
input adc_clk,
input [ 3:0] adc_rx_sof,
input [ 63:0] adc_rx_data,
input adc_os_clk,
input [ 3:0] adc_rx_os_sof,
input [ 63:0] adc_rx_os_data,
output [ 63:0] adc_data,
output adc_os_valid,
output [ 63:0] adc_os_data,
// transmit
input dac_clk,
output [127:0] dac_tx_data,
input [127:0] dac_data);
// internal signals
wire [ 63:0] adc_rx_data_s;
wire [ 63:0] adc_rx_os_data_s;
// delineating
assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data_s[((8* 6)+7):(8* 6)];
assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data_s[((8* 7)+7):(8* 7)];
assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data_s[((8* 4)+7):(8* 4)];
assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data_s[((8* 5)+7):(8* 5)];
assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data_s[((8* 2)+7):(8* 2)];
assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data_s[((8* 3)+7):(8* 3)];
assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data_s[((8* 0)+7):(8* 0)];
assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data_s[((8* 1)+7):(8* 1)];
assign adc_os_valid = 'd1;
assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data_s[((8* 6)+7):(8* 6)];
assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data_s[((8* 7)+7):(8* 7)];
assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data_s[((8* 4)+7):(8* 4)];
assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data_s[((8* 5)+7):(8* 5)];
assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data_s[((8* 2)+7):(8* 2)];
assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data_s[((8* 3)+7):(8* 3)];
assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data_s[((8* 0)+7):(8* 0)];
assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data_s[((8* 1)+7):(8* 1)];
assign dac_tx_data[((8*15)+7):(8*15)] = dac_data[((8*14)+7):(8*14)];
assign dac_tx_data[((8*14)+7):(8*14)] = dac_data[((8*15)+7):(8*15)];
assign dac_tx_data[((8*13)+7):(8*13)] = dac_data[((8*12)+7):(8*12)];
assign dac_tx_data[((8*12)+7):(8*12)] = dac_data[((8*13)+7):(8*13)];
assign dac_tx_data[((8*11)+7):(8*11)] = dac_data[((8*10)+7):(8*10)];
assign dac_tx_data[((8*10)+7):(8*10)] = dac_data[((8*11)+7):(8*11)];
assign dac_tx_data[((8* 9)+7):(8* 9)] = dac_data[((8* 8)+7):(8* 8)];
assign dac_tx_data[((8* 8)+7):(8* 8)] = dac_data[((8* 9)+7):(8* 9)];
assign dac_tx_data[((8* 7)+7):(8* 7)] = dac_data[((8* 6)+7):(8* 6)];
assign dac_tx_data[((8* 6)+7):(8* 6)] = dac_data[((8* 7)+7):(8* 7)];
assign dac_tx_data[((8* 5)+7):(8* 5)] = dac_data[((8* 4)+7):(8* 4)];
assign dac_tx_data[((8* 4)+7):(8* 4)] = dac_data[((8* 5)+7):(8* 5)];
assign dac_tx_data[((8* 3)+7):(8* 3)] = dac_data[((8* 2)+7):(8* 2)];
assign dac_tx_data[((8* 2)+7):(8* 2)] = dac_data[((8* 3)+7):(8* 3)];
assign dac_tx_data[((8* 1)+7):(8* 1)] = dac_data[((8* 0)+7):(8* 0)];
assign dac_tx_data[((8* 0)+7):(8* 0)] = dac_data[((8* 1)+7):(8* 1)];
// instantiations
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if i_xcvr_rx_if (
.rx_clk (adc_clk),
.rx_ip_sof (adc_rx_sof),
.rx_ip_data (adc_rx_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (adc_rx_data_s[((n*32)+31):(n*32)]));
ad_xcvr_rx_if i_xcvr_rx_os_if (
.rx_clk (adc_os_clk),
.rx_ip_sof (adc_rx_os_sof),
.rx_ip_data (adc_rx_os_data[((n*32)+31):(n*32)]),
.rx_sof (),
.rx_data (adc_rx_os_data_s[((n*32)+31):(n*32)]));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9379
adi_ip_files axi_ad9379 [list \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
"axi_ad9379_if.v" \
"axi_ad9379_rx_channel.v" \
"axi_ad9379_rx.v" \
"axi_ad9379_rx_os.v" \
"axi_ad9379_tx_channel.v" \
"axi_ad9379_tx.v" \
"axi_ad9379.v" ]
adi_ip_properties axi_ad9379
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9379_rx #(
parameter DATAPATH_DISABLE = 0,
parameter ID = 0) (
// adc interface
output adc_rst,
input adc_clk,
input [ 63:0] adc_data,
// dma interface
output adc_enable_i0,
output adc_valid_i0,
output [ 15:0] adc_data_i0,
output adc_enable_q0,
output adc_valid_q0,
output [ 15:0] adc_data_q0,
output adc_enable_i1,
output adc_valid_i1,
output [ 15:0] adc_data_i1,
output adc_enable_q1,
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
// internal signals
wire [ 15:0] adc_data_iq_i0_s;
wire [ 15:0] adc_data_iq_q0_s;
wire [ 15:0] adc_data_iq_i1_s;
wire [ 15:0] adc_data_iq_q1_s;
wire [ 3:0] up_adc_pn_err_s;
wire [ 3:0] up_adc_pn_oos_s;
wire [ 3:0] up_adc_or_s;
wire [ 4:0] up_wack_s;
wire [ 4:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:4];
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
end
end
// channel width is 32 bits
assign adc_valid_i0 = 1'b1;
assign adc_valid_q0 = 1'b1;
assign adc_valid_i1 = 1'b1;
assign adc_valid_q1 = 1'b1;
// channel 0 (i)
axi_ad9379_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID ('h01),
.CHANNEL_ID (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (1'b1),
.adc_data_in (adc_data[15:0]),
.adc_valid_out (),
.adc_data_out (adc_data_i0),
.adc_data_iq_in (adc_data_iq_q0_s),
.adc_data_iq_out (adc_data_iq_i0_s),
.adc_enable (adc_enable_i0),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel 1 (q)
axi_ad9379_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID ('h01),
.CHANNEL_ID (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (1'b1),
.adc_data_in (adc_data[31:16]),
.adc_valid_out (),
.adc_data_out (adc_data_q0),
.adc_data_iq_in (adc_data_iq_i0_s),
.adc_data_iq_out (adc_data_iq_q0_s),
.adc_enable (adc_enable_q0),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// channel 2 (i)
axi_ad9379_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID ('h01),
.CHANNEL_ID (2),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_2 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (1'b1),
.adc_data_in (adc_data[47:32]),
.adc_valid_out (),
.adc_data_out (adc_data_i1),
.adc_data_iq_in (adc_data_iq_q1_s),
.adc_data_iq_out (adc_data_iq_i1_s),
.adc_enable (adc_enable_i1),
.up_adc_pn_err (up_adc_pn_err_s[2]),
.up_adc_pn_oos (up_adc_pn_oos_s[2]),
.up_adc_or (up_adc_or_s[2]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// channel 3 (q)
axi_ad9379_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID ('h01),
.CHANNEL_ID (3),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.DATA_WIDTH (16))
i_rx_channel_3 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid_in (1'b1),
.adc_data_in (adc_data[63:48]),
.adc_valid_out (),
.adc_data_out (adc_data_q1),
.adc_data_iq_in (adc_data_iq_i1_s),
.adc_data_iq_out (adc_data_iq_q1_s),
.adc_enable (adc_enable_q1),
.up_adc_pn_err (up_adc_pn_err_s[3]),
.up_adc_pn_oos (up_adc_pn_oos_s[3]),
.up_adc_or (up_adc_or_s[3]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// common processor control
up_adc_common #(
.COMMON_ID ('h00),
.ID (ID))
i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_adc_ce (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9379_rx_channel #(
parameter Q_OR_I_N = 0,
parameter COMMON_ID = 0,
parameter CHANNEL_ID = 0,
parameter DATAPATH_DISABLE = 0,
parameter DATA_WIDTH = 32) (
// adc interface
input adc_clk,
input adc_rst,
input adc_valid_in,
input [(DATA_WIDTH-1):0] adc_data_in,
output adc_valid_out,
output [(DATA_WIDTH-1):0] adc_data_out,
input [(DATA_WIDTH-1):0] adc_data_iq_in,
output [(DATA_WIDTH-1):0] adc_data_iq_out,
output adc_enable,
// channel interface
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
localparam NUM_OF_SAMPLES = DATA_WIDTH/16;
// internal signals
wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s;
wire [(DATA_WIDTH-1):0] adc_dfmt_data_s;
wire [(NUM_OF_SAMPLES-1):0] adc_dcfilter_valid_s;
wire [(DATA_WIDTH-1):0] adc_dcfilter_data_s;
wire [(NUM_OF_SAMPLES-1):0] adc_valid_out_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire adc_dcfilt_enb_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire adc_iqcor_enb_s;
wire [15:0] adc_iqcor_coeff_1_s;
wire [15:0] adc_iqcor_coeff_2_s;
// variables
genvar n;
// iq correction inputs
assign adc_pn_oos_s = 1'b1;
assign adc_pn_err_s = 1'b0;
generate
for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_datafmt
if (DATAPATH_DISABLE == 1) begin
assign adc_dfmt_valid_s[n] = adc_valid_in;
assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in[((16*n)+15):(16*n)];
end else begin
ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid_in),
.data (adc_data_in[((16*n)+15):(16*n)]),
.valid_out (adc_dfmt_valid_s[n]),
.data_out (adc_dfmt_data_s[((16*n)+15):(16*n)]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
end
endgenerate
generate
for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_dcfilter
if (DATAPATH_DISABLE == 1) begin
assign adc_dcfilter_valid_s[n] = adc_dfmt_valid_s[n];
assign adc_dcfilter_data_s[((16*n)+15):(16*n)] = adc_dfmt_data_s[((16*n)+15):(16*n)];
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (adc_dfmt_valid_s[n]),
.data (adc_dfmt_data_s[((16*n)+15):(16*n)]),
.valid_out (adc_dcfilter_valid_s[n]),
.data_out (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
end
endgenerate
assign adc_valid_out = adc_valid_out_s[0];
assign adc_data_iq_out = adc_dcfilter_data_s;
generate
for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_iqcor
if (DATAPATH_DISABLE == 1) begin
assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
.clk (adc_clk),
.valid (adc_dcfilter_valid_s[n]),
.data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
.data_iq (adc_data_iq_in[((16*n)+15):(16*n)]),
.valid_out (adc_valid_out_s[n]),
.data_out (adc_data_out[((16*n)+15):(16*n)]),
.iqcor_enable (adc_iqcor_enb_s),
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
end
end
endgenerate
up_adc_channel #(
.COMMON_ID (COMMON_ID),
.CHANNEL_ID (CHANNEL_ID))
i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (adc_iqcor_enb_s),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (1'd0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9379_rx_os #(
parameter DATAPATH_DISABLE = 0,
parameter ID = 0) (
// adc interface
output adc_os_rst,
input adc_os_clk,
input adc_os_valid,
input [ 63:0] adc_os_data,
// dma interface
output adc_os_enable_i0,
output adc_os_valid_i0,
output [ 31:0] adc_os_data_i0,
output adc_os_enable_q0,
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
// internal signals
wire [ 31:0] adc_os_data_iq_i0_s;
wire [ 31:0] adc_os_data_iq_q0_s;
wire [ 1:0] up_adc_pn_err_s;
wire [ 1:0] up_adc_pn_oos_s;
wire [ 1:0] up_adc_or_s;
wire [ 2:0] up_wack_s;
wire [ 2:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:2];
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_status_pn_err <= | up_adc_pn_err_s;
up_status_pn_oos <= | up_adc_pn_oos_s;
up_status_or <= | up_adc_or_s;
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
end
end
// channel o/s (i)
axi_ad9379_rx_channel #(
.Q_OR_I_N (0),
.COMMON_ID ('h21),
.CHANNEL_ID (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.DATA_WIDTH (32))
i_rx_os_channel_0 (
.adc_clk (adc_os_clk),
.adc_rst (adc_os_rst),
.adc_valid_in (adc_os_valid),
.adc_data_in (adc_os_data[31:0]),
.adc_valid_out (adc_os_valid_i0),
.adc_data_out (adc_os_data_i0),
.adc_data_iq_in (adc_os_data_iq_q0_s),
.adc_data_iq_out (adc_os_data_iq_i0_s),
.adc_enable (adc_os_enable_i0),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel o/s (q)
axi_ad9379_rx_channel #(
.Q_OR_I_N (1),
.COMMON_ID ('h21),
.CHANNEL_ID (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.DATA_WIDTH (32))
i_rx_os_channel_1 (
.adc_clk (adc_os_clk),
.adc_rst (adc_os_rst),
.adc_valid_in (adc_os_valid),
.adc_data_in (adc_os_data[63:32]),
.adc_valid_out (adc_os_valid_q0),
.adc_data_out (adc_os_data_q0),
.adc_data_iq_in (adc_os_data_iq_i0_s),
.adc_data_iq_out (adc_os_data_iq_q0_s),
.adc_enable (adc_os_enable_q0),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// common processor control
up_adc_common #(
.COMMON_ID ('h20),
.ID (ID))
i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_os_clk),
.adc_rst (adc_os_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_os_dovf),
.adc_status_unf (adc_os_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_adc_ce (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8'd3),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9379_tx #(
parameter DATAPATH_DISABLE = 0,
parameter ID = 0) (
// dac interface
output dac_rst,
input dac_clk,
output [127:0] dac_data,
// master/slave
input dac_sync_in,
output dac_sync_out,
// dma interface
output dac_enable_i0,
output dac_valid_i0,
input [ 31:0] dac_data_i0,
output dac_enable_q0,
output dac_valid_q0,
input [ 31:0] dac_data_q0,
output dac_enable_i1,
output dac_valid_i1,
input [ 31:0] dac_data_i1,
output dac_enable_q1,
output dac_valid_q1,
input [ 31:0] dac_data_q1,
input dac_dovf,
input dac_dunf,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// internal registers
reg dac_data_sync = 'd0;
// internal signals
wire dac_data_sync_s;
wire [ 31:0] dac_data_iq_i0_s;
wire [ 31:0] dac_data_iq_q0_s;
wire [ 31:0] dac_data_iq_i1_s;
wire [ 31:0] dac_data_iq_q1_s;
wire dac_dds_format_s;
wire [ 4:0] up_wack_s;
wire [ 4:0] up_rack_s;
wire [ 31:0] up_rdata_s[0:4];
// master/slave
assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
always @(posedge dac_clk) begin
dac_data_sync <= dac_data_sync_s;
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= | up_wack_s;
up_rack <= | up_rack_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
up_rdata_s[3] | up_rdata_s[4];
end
end
// dac channel
assign dac_valid_i0 = 1'b1;
axi_ad9379_tx_channel #(
.CHANNEL_ID (0),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_0 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in (dac_data_i0),
.dac_data_out (dac_data[31:0]),
.dac_data_iq_in (dac_data_iq_q0_s),
.dac_data_iq_out (dac_data_iq_i0_s),
.dac_enable (dac_enable_i0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// dac channel
assign dac_valid_q0 = 1'b1;
axi_ad9379_tx_channel #(
.CHANNEL_ID (1),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_1 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in (dac_data_q0),
.dac_data_out (dac_data[63:32]),
.dac_data_iq_in (dac_data_iq_i0_s),
.dac_data_iq_out (dac_data_iq_q0_s),
.dac_enable (dac_enable_q0),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// dac channel
assign dac_valid_i1 = 1'b1;
axi_ad9379_tx_channel #(
.CHANNEL_ID (2),
.Q_OR_I_N (0),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_2 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in (dac_data_i1),
.dac_data_out (dac_data[95:64]),
.dac_data_iq_in (dac_data_iq_q1_s),
.dac_data_iq_out (dac_data_iq_i1_s),
.dac_enable (dac_enable_i1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// dac channel
assign dac_valid_q1 = 1'b1;
axi_ad9379_tx_channel #(
.CHANNEL_ID (3),
.Q_OR_I_N (1),
.DATAPATH_DISABLE (DATAPATH_DISABLE))
i_tx_channel_3 (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_data_in (dac_data_q1),
.dac_data_out (dac_data[127:96]),
.dac_data_iq_in (dac_data_iq_i1_s),
.dac_data_iq_out (dac_data_iq_q1_s),
.dac_enable (dac_enable_q1),
.dac_data_sync (dac_data_sync),
.dac_dds_format (dac_dds_format_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// dac common processor interface
up_dac_common #(.ID (ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_out),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_dds_format_s),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd2),
.up_dac_ce (),
.up_pps_rcounter(32'h0),
.up_pps_status(1'b0),
.up_pps_irq_mask(),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[4]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[4]),
.up_rack (up_rack_s[4]));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9379_tx_channel #(
parameter CHANNEL_ID = 32'h0,
parameter Q_OR_I_N = 0,
parameter DATAPATH_DISABLE = 0) (
// dac interface
input dac_clk,
input dac_rst,
input [31:0] dac_data_in,
output [31:0] dac_data_out,
input [31:0] dac_data_iq_in,
output reg [31:0] dac_data_iq_out,
// processor interface
output reg dac_enable,
input dac_data_sync,
input dac_dds_format,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal registers
reg [31:0] dac_pat_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [31:0] dac_dds_data = 'd0;
// internal signals
wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
wire dac_iqcor_enb_s;
wire [15:0] dac_iqcor_coeff_1_s;
wire [15:0] dac_iqcor_coeff_2_s;
// dac iq correction
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_data_out = dac_data_iq_out;
end else begin
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_1 (
.clk (dac_clk),
.valid (1'b1),
.data_in (dac_data_iq_out[31:16]),
.data_iq (dac_data_iq_in[31:16]),
.valid_out (),
.data_out (dac_data_out[31:16]),
.iqcor_enable (dac_iqcor_enb_s),
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_0 (
.clk (dac_clk),
.valid (1'b1),
.data_in (dac_data_iq_out[15:0]),
.data_iq (dac_data_iq_in[15:0]),
.valid_out (),
.data_out (dac_data_out[15:0]),
.iqcor_enable (dac_iqcor_enb_s),
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
end
endgenerate
// dac mux
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h3: dac_data_iq_out <= 32'd0;
4'h2: dac_data_iq_out <= dac_data_in;
4'h1: dac_data_iq_out <= dac_pat_data;
default: dac_data_iq_out <= dac_dds_data;
endcase
end
// pattern
always @(posedge dac_clk) begin
dac_pat_data <= {dac_pat_data_2_s, dac_pat_data_1_s};
end
// dds
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0_0 <= dac_dds_init_1_s;
dac_dds_phase_0_1 <= dac_dds_init_2_s;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[14:0], 1'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[14:0], 1'd0};
dac_dds_data <= 32'd0;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= {dac_dds_data_1_s, dac_dds_data_0_s};
end
end
// dds
generate
if (DATAPATH_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s));
ad_dds i_dds_1 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_1_s));
end
endgenerate
// single channel processor
up_dac_channel #(.CHANNEL_ID (CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iq_mode (),
.dac_iqcor_enb (dac_iqcor_enb_s),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************