diff --git a/projects/fmcomms2/c5soc/system_bd.qsys b/projects/fmcomms2/c5soc/system_bd.qsys new file mode 100755 index 000000000..b303ee956 --- /dev/null +++ b/projects/fmcomms2/c5soc/system_bd.qsys @@ -0,0 +1,1983 @@ + + + + + + + + + + + + + + + fmcjesdadc1_a5soc.qpf + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0x000000000000000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Avalon-MM Bidirectional + + + + + + + + No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,Yes,Yes,No,No,No,Yes,No,Yes,No,Yes,Yes,No,No,No,No,No,No,No,Yes,No,No,No,No,Yes,Yes,Yes,Yes,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $${FILENAME}_sys_int_mem + + ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Automatic Switchover + + + + + + + Create an adjpllin signal to connect with an upstream PLL + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/fmcomms2/c5soc/system_constr.sdc b/projects/fmcomms2/c5soc/system_constr.sdc new file mode 100755 index 000000000..d777aa616 --- /dev/null +++ b/projects/fmcomms2/c5soc/system_constr.sdc @@ -0,0 +1,25 @@ + +create_clock -period "10.000 ns" -name clk_100m [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name clk_250m [get_ports {ref_clk}] +create_clock -period "6.666 ns" -name clk_150m [get_pins {i_system_bd|sys_hps|fpga_interfaces|clocks_resets|h2f_user0_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set clk_148m [get_clocks {i_system_bd|sys_hdmi_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] +set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] + +set_false_path -from clk_100m -to clk_150m +set_false_path -from clk_100m -to $clk_148m +set_false_path -from clk_100m -to $clk_rxlink +set_false_path -from clk_150m -to clk_100m +set_false_path -from clk_150m -to $clk_148m +set_false_path -from clk_150m -to $clk_rxlink +set_false_path -from $clk_rxlink -to clk_100m +set_false_path -from $clk_rxlink -to clk_150m +set_false_path -from $clk_rxlink -to $clk_148m +set_false_path -from $clk_148m -to clk_100m +set_false_path -from $clk_148m -to clk_150m +set_false_path -from $clk_148m -to $clk_rxlink + + diff --git a/projects/fmcomms2/c5soc/system_project.tcl b/projects/fmcomms2/c5soc/system_project.tcl new file mode 100755 index 000000000..30d9cbca7 --- /dev/null +++ b/projects/fmcomms2/c5soc/system_project.tcl @@ -0,0 +1,69 @@ + +load_package flow + +source ../../scripts/adi_env.tcl +project_new fmcjesdadc1_a5soc -overwrite + +set_global_assignment -name FAMILY "Arria V" +set_global_assignment -name DEVICE 5ASTFD5K3F40I3ES +set_global_assignment -name TOP_LEVEL_ENTITY system_top +set_global_assignment -name SDC_FILE system_constr.sdc +set_global_assignment -name QSYS_FILE system_bd.qsys +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v +set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v +set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v +set_global_assignment -name VERILOG_FILE system_top.v + +source $ad_hdl_dir/projects/common/a5soc/a5soc_system_assign.tcl + +# reference clock + +set_location_assignment PIN_AG32 -to ref_clk +set_location_assignment PIN_AG33 -to "ref_clk(n)" +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to ref_clk +set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to ref_clk +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk + +# lane data + +set_location_assignment PIN_AW37 -to rx_data[0] +set_location_assignment PIN_AW36 -to "rx_data[0](n)" +set_location_assignment PIN_AP39 -to rx_data[1] +set_location_assignment PIN_AP38 -to "rx_data[1](n)" +set_location_assignment PIN_AM39 -to rx_data[2] +set_location_assignment PIN_AM38 -to "rx_data[2](n)" +set_location_assignment PIN_AH39 -to rx_data[3] +set_location_assignment PIN_AH38 -to "rx_data[3](n)" +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[2] +set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[3] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[2] +set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[3] + +# jesd signals + +set_location_assignment PIN_A29 -to rx_sync +set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sync + +set_location_assignment PIN_A28 -to rx_sysref +set_instance_assignment -name IO_STANDARD "2.5 V" -to rx_sysref + +# spi + +set_location_assignment PIN_C29 -to spi_csn +set_location_assignment PIN_B28 -to spi_clk +set_location_assignment PIN_C32 -to spi_sdio + +set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn +set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio + +#set_global_assignment -name SEARCH_PATH db/ip/system_bd +#set_global_assignment -name SEARCH_PATH db/ip/system_bd/submodules +#set_global_assignment -name SEARCH_PATH db/ip/system_bd/submodules/sequencer + +execute_flow -compile + diff --git a/projects/fmcomms2/c5soc/system_timing.tcl b/projects/fmcomms2/c5soc/system_timing.tcl new file mode 100755 index 000000000..e1f355d44 --- /dev/null +++ b/projects/fmcomms2/c5soc/system_timing.tcl @@ -0,0 +1,3 @@ + +report_timing -detail path_only -npaths 20 -file timing_impl.log + diff --git a/projects/fmcomms2/c5soc/system_top.v b/projects/fmcomms2/c5soc/system_top.v new file mode 100755 index 000000000..df4798e76 --- /dev/null +++ b/projects/fmcomms2/c5soc/system_top.v @@ -0,0 +1,611 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + sys_clk, + + // hps + + ddr3_a, + ddr3_ba, + ddr3_ck_p, + ddr3_ck_n, + ddr3_cke, + ddr3_cs_n, + ddr3_ras_n, + ddr3_cas_n, + ddr3_we_n, + ddr3_reset_n, + ddr3_dq, + ddr3_dqs_p, + ddr3_dqs_n, + ddr3_odt, + ddr3_dm, + ddr3_oct_rzqin, + eth1_tx_clk, + eth1_tx_ctl, + eth1_txd0, + eth1_txd1, + eth1_txd2, + eth1_txd3, + eth1_rx_clk, + eth1_rx_ctl, + eth1_rxd0, + eth1_rxd1, + eth1_rxd2, + eth1_rxd3, + eth1_mdc, + eth1_mdio, + qspi_ss0, + qspi_clk, + qspi_io0, + qspi_io1, + qspi_io2, + qspi_io3, + sdio_clk, + sdio_cmd, + sdio_d0, + sdio_d1, + sdio_d2, + sdio_d3, + usb1_clk, + usb1_stp, + usb1_dir, + usb1_nxt, + usb1_d0, + usb1_d1, + usb1_d2, + usb1_d3, + usb1_d4, + usb1_d5, + usb1_d6, + usb1_d7, + uart0_rx, + uart0_tx, + uart1_rx, + uart1_tx, + i2c0_scl, + i2c0_sda, + trace_clk, + trace_d0, + trace_d1, + trace_d2, + trace_d3, + trace_d4, + trace_d5, + trace_d6, + trace_d7, + gpio_gpio00, + gpio_gpio17, + gpio_gpio18, + gpio_gpio22, + gpio_gpio24, + gpio_gpio26, + gpio_gpio27, + gpio_gpio35, + gpio_gpio40, + gpio_gpio41, + gpio_gpio42, + gpio_gpio43, + + // board gpio + + led, + push_buttons, + dip_switches, + + // hdmi + + hdmi_out_clk, + hdmi_data, + + // lane interface + + ref_clk, + rx_data, + rx_sync, + rx_sysref, + + // spi + + spi_csn, + spi_clk, + spi_sdio); + + // clock and resets + + input sys_clk; + + // hps + + output [ 14:0] ddr3_a; + output [ 2:0] ddr3_ba; + output ddr3_ck_p; + output ddr3_ck_n; + output ddr3_cke; + output ddr3_cs_n; + output ddr3_ras_n; + output ddr3_cas_n; + output ddr3_we_n; + output ddr3_reset_n; + inout [ 39:0] ddr3_dq; + inout [ 4:0] ddr3_dqs_p; + inout [ 4:0] ddr3_dqs_n; + output ddr3_odt; + output [ 4:0] ddr3_dm; + input ddr3_oct_rzqin; + output eth1_tx_clk; + output eth1_tx_ctl; + output eth1_txd0; + output eth1_txd1; + output eth1_txd2; + output eth1_txd3; + input eth1_rx_clk; + input eth1_rx_ctl; + input eth1_rxd0; + input eth1_rxd1; + input eth1_rxd2; + input eth1_rxd3; + output eth1_mdc; + inout eth1_mdio; + output qspi_ss0; + output qspi_clk; + inout qspi_io0; + inout qspi_io1; + inout qspi_io2; + inout qspi_io3; + output sdio_clk; + inout sdio_cmd; + inout sdio_d0; + inout sdio_d1; + inout sdio_d2; + inout sdio_d3; + input usb1_clk; + output usb1_stp; + input usb1_dir; + input usb1_nxt; + inout usb1_d0; + inout usb1_d1; + inout usb1_d2; + inout usb1_d3; + inout usb1_d4; + inout usb1_d5; + inout usb1_d6; + inout usb1_d7; + input uart0_rx; + output uart0_tx; + input uart1_rx; + output uart1_tx; + inout i2c0_scl; + inout i2c0_sda; + output trace_clk; + output trace_d0; + output trace_d1; + output trace_d2; + output trace_d3; + output trace_d4; + output trace_d5; + output trace_d6; + output trace_d7; + inout gpio_gpio00; + inout gpio_gpio17; + inout gpio_gpio18; + inout gpio_gpio22; + inout gpio_gpio24; + inout gpio_gpio26; + inout gpio_gpio27; + inout gpio_gpio35; + inout gpio_gpio40; + inout gpio_gpio41; + inout gpio_gpio42; + inout gpio_gpio43; + + // board gpio + + output [ 3:0] led; + input [ 3:0] push_buttons; + input [ 3:0] dip_switches; + + // hdmi + + output hdmi_out_clk; + output [ 15:0] hdmi_data; + + // lane interface + + input ref_clk; + input [ 3:0] rx_data; + output rx_sync; + output rx_sysref; + + // spi + + output spi_csn; + output spi_clk; + inout spi_sdio; + + // internal registers + + reg rx_sysref_m1 = 'd0; + reg rx_sysref_m2 = 'd0; + reg rx_sysref_m3 = 'd0; + reg rx_sysref = 'd0; + reg dma0_wr = 'd0; + reg [ 63:0] dma0_wdata = 'd0; + reg dma1_wr = 'd0; + reg [ 63:0] dma1_wdata = 'd0; + reg [ 63:0] sys_hdmi_pll_reconfig_in = 'd0; + reg [ 63:0] sys_hdmi_pll_reconfig_reconfig_in = 'd0; + + // internal clocks and resets + + wire sys_resetn; + wire rx_clk; + wire adc0_clk; + wire adc1_clk; + + // internal signals + + wire spi_mosi; + wire spi_miso; + wire adc0_enable_a_s; + wire [ 31:0] adc0_data_a_s; + wire adc0_enable_b_s; + wire [ 31:0] adc0_data_b_s; + wire adc0_dovf_s; + wire adc1_enable_a_s; + wire [ 31:0] adc1_data_a_s; + wire adc1_enable_b_s; + wire [ 31:0] adc1_data_b_s; + wire adc1_dovf_s; + wire [ 3:0] rx_ip_sof_s; + wire [127:0] rx_ip_data_s; + wire [127:0] rx_data_s; + wire rx_sw_rstn_s; + wire rx_sysref_s; + wire rx_err_s; + wire rx_ready_s; + wire [ 3:0] rx_rst_state_s; + wire rx_lane_aligned_s; + wire [ 3:0] rx_analog_reset_s; + wire [ 3:0] rx_digital_reset_s; + wire [ 3:0] rx_cdr_locked_s; + wire [ 3:0] rx_cal_busy_s; + wire rx_pll_locked_s; + wire [ 15:0] rx_xcvr_status_s; + wire [ 63:0] sys_hdmi_pll_reconfig_out; + wire [ 63:0] sys_hdmi_pll_reconfig_reconfig_out; + + // instantiations + + always @(posedge rx_clk) begin + rx_sysref_m1 <= rx_sysref_s; + rx_sysref_m2 <= rx_sysref_m1; + rx_sysref_m3 <= rx_sysref_m2; + rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3; + end + + always @(posedge rx_clk) begin + dma0_wr <= adc0_enable_a_s & adc0_enable_b_s; + dma0_wdata <= { adc0_data_b_s[31:16], + adc0_data_a_s[31:16], + adc0_data_b_s[15: 0], + adc0_data_a_s[15: 0]}; + dma1_wr <= adc1_enable_a_s & adc1_enable_b_s; + dma1_wdata <= { adc1_data_b_s[31:16], + adc1_data_a_s[31:16], + adc1_data_b_s[15: 0], + adc1_data_a_s[15: 0]}; + end + + sld_signaltap #( + .sld_advanced_trigger_entity ("basic,1,"), + .sld_data_bits (5), + .sld_data_bit_cntr_bits (8), + .sld_enable_advanced_trigger (0), + .sld_mem_address_bits (10), + .sld_node_crc_bits (32), + .sld_node_crc_hiword (10311), + .sld_node_crc_loword (14297), + .sld_node_info (1076736), + .sld_ram_block_type ("AUTO"), + .sld_sample_depth (1024), + .sld_storage_qualifier_gap_record (0), + .sld_storage_qualifier_mode ("OFF"), + .sld_trigger_bits (2), + .sld_trigger_in_enabled (0), + .sld_trigger_level (1), + .sld_trigger_level_pipeline (1)) + i_signaltap ( + .acq_clk (sys_clk), + .acq_data_in ({ spi_csn, + spi_clk, + spi_mosi, + spi_miso, + spi_sdio}), + .acq_trigger_in ({spi_csn, spi_clk})); + + /* + sld_signaltap #( + .sld_advanced_trigger_entity ("basic,1,"), + .sld_data_bits (130), + .sld_data_bit_cntr_bits (8), + .sld_enable_advanced_trigger (0), + .sld_mem_address_bits (10), + .sld_node_crc_bits (32), + .sld_node_crc_hiword (10311), + .sld_node_crc_loword (14297), + .sld_node_info (1076736), + .sld_ram_block_type ("AUTO"), + .sld_sample_depth (1024), + .sld_storage_qualifier_gap_record (0), + .sld_storage_qualifier_mode ("OFF"), + .sld_trigger_bits (2), + .sld_trigger_in_enabled (0), + .sld_trigger_level (1), + .sld_trigger_level_pipeline (1)) + i_signaltap ( + .acq_clk (rx_clk), + .acq_data_in ({ rx_sysref, + rx_sync, + adc1_data_b_s, + adc1_data_a_s, + adc0_data_b_s, + adc0_data_a_s}), + .acq_trigger_in ({rx_sysref, rx_sync})); + + */ + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_align_1 + ad_jesd_align i_jesd_align ( + .rx_clk (rx_clk), + .rx_sof (rx_ip_sof_s), + .rx_ip_data (rx_ip_data_s[n*32+31:n*32]), + .rx_data (rx_data_s[n*32+31:n*32])); + end + endgenerate + + assign rx_xcvr_status_s[15:15] = 1'd0; + assign rx_xcvr_status_s[14:14] = rx_sync; + assign rx_xcvr_status_s[13:13] = rx_ready_s; + assign rx_xcvr_status_s[12:12] = rx_pll_locked_s; + assign rx_xcvr_status_s[11: 8] = rx_rst_state_s; + assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s; + assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s; + + ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst ( + .rx_clk (rx_clk), + .rx_rstn (sys_resetn), + .rx_sw_rstn (rx_sw_rstn_s), + .rx_pll_locked (rx_pll_locked_s), + .rx_cal_busy (rx_cal_busy_s), + .rx_cdr_locked (rx_cdr_locked_s), + .rx_analog_reset (rx_analog_reset_s), + .rx_digital_reset (rx_digital_reset_s), + .rx_ready (rx_ready_s), + .rx_rst_state (rx_rst_state_s)); + + fmcjesdadc1_spi i_fmcjesdadc1_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + // pipe line to fix timing + + always @(posedge sys_clk) begin + sys_hdmi_pll_reconfig_in <= sys_hdmi_pll_reconfig_reconfig_out; + sys_hdmi_pll_reconfig_reconfig_in <= sys_hdmi_pll_reconfig_out; + end + + system_bd i_system_bd ( + .memory_mem_a (ddr3_a), + .memory_mem_ba (ddr3_ba), + .memory_mem_ck (ddr3_ck_p), + .memory_mem_ck_n (ddr3_ck_n), + .memory_mem_cke (ddr3_cke), + .memory_mem_cs_n (ddr3_cs_n), + .memory_mem_ras_n (ddr3_ras_n), + .memory_mem_cas_n (ddr3_cas_n), + .memory_mem_we_n (ddr3_we_n), + .memory_mem_reset_n (ddr3_reset_n), + .memory_mem_dq (ddr3_dq), + .memory_mem_dqs (ddr3_dqs_p), + .memory_mem_dqs_n (ddr3_dqs_n), + .memory_mem_odt (ddr3_odt), + .memory_mem_dm (ddr3_dm), + .memory_oct_rzqin (ddr3_oct_rzqin), + .clk_clk (sys_clk), + .reset_reset_n (sys_resetn), + .axi_ad9250_0_xcvr_clk_clk (rx_clk), + .axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]), + .axi_ad9250_0_adc_clock_clk (adc0_clk), + .axi_ad9250_0_adc_dma_if_adc_valid_a (), + .axi_ad9250_0_adc_dma_if_adc_enable_a (adc0_enable_a_s), + .axi_ad9250_0_adc_dma_if_adc_data_a (adc0_data_a_s), + .axi_ad9250_0_adc_dma_if_adc_valid_b (), + .axi_ad9250_0_adc_dma_if_adc_enable_b (adc0_enable_b_s), + .axi_ad9250_0_adc_dma_if_adc_data_b (adc0_data_b_s), + .axi_ad9250_0_adc_dma_if_adc_dovf (adc0_dovf_s), + .axi_ad9250_0_adc_dma_if_adc_dunf (1'b0), + .axi_dmac_0_fifo_wr_clock_clk (adc0_clk), + .axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s), + .axi_dmac_0_fifo_wr_if_wren (dma0_wr), + .axi_dmac_0_fifo_wr_if_data (dma0_wdata), + .axi_dmac_0_fifo_wr_if_sync (1'b1), + .axi_ad9250_1_xcvr_clk_clk (rx_clk), + .axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]), + .axi_ad9250_1_adc_clock_clk (adc1_clk), + .axi_ad9250_1_adc_dma_if_adc_valid_a (), + .axi_ad9250_1_adc_dma_if_adc_enable_a (adc1_enable_a_s), + .axi_ad9250_1_adc_dma_if_adc_data_a (adc1_data_a_s), + .axi_ad9250_1_adc_dma_if_adc_valid_b (), + .axi_ad9250_1_adc_dma_if_adc_enable_b (adc1_enable_b_s), + .axi_ad9250_1_adc_dma_if_adc_data_b (adc1_data_b_s), + .axi_ad9250_1_adc_dma_if_adc_dovf (adc1_dovf_s), + .axi_ad9250_1_adc_dma_if_adc_dunf (1'b0), + .axi_dmac_1_fifo_wr_clock_clk (adc1_clk), + .axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s), + .axi_dmac_1_fifo_wr_if_wren (dma1_wr), + .axi_dmac_1_fifo_wr_if_data (dma1_wdata), + .axi_dmac_1_fifo_wr_if_sync (1'b1), + .sys_jesd204b_s1_ref_clk_in_clk_clk (ref_clk), + .sys_jesd204b_s1_rx_clk_out_clk_clk (rx_clk), + .sys_jesd204b_s1_jesd204_rx_link_data (rx_ip_data_s), + .sys_jesd204b_s1_jesd204_rx_link_valid (), + .sys_jesd204b_s1_jesd204_rx_link_ready (1'b1), + .sys_jesd204b_s1_alldev_lane_aligned_export (rx_lane_aligned_s), + .sys_jesd204b_s1_sysref_export (rx_sysref), + .sys_jesd204b_s1_jesd204_rx_frame_error_export (rx_err_s), + .sys_jesd204b_s1_dev_lane_aligned_export (rx_lane_aligned_s), + .sys_jesd204b_s1_dev_sync_n_export (rx_sync), + .sys_jesd204b_s1_sof_export (rx_ip_sof_s), + .sys_jesd204b_s1_rx_serial_data_rx_serial_data (rx_data), + .sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s), + .sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s), + .sys_jesd204b_s1_rx_islockedtodata_export (rx_cdr_locked_s), + .sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s), + .sys_hps_spim0_txd (spi_mosi), + .sys_hps_spim0_rxd (spi_miso), + .sys_hps_spim0_ss_in_n (1'b1), + .sys_hps_spim0_ssi_oe_n (), + .sys_hps_spim0_ss_0_n (spi_csn), + .sys_hps_spim0_ss_1_n (), + .sys_hps_spim0_ss_2_n (), + .sys_hps_spim0_ss_3_n (), + .sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s), + .sys_hps_spim0_sclk_out_clk (spi_clk), + .sys_hps_f2h_stm_hw_events_stm_hwevents ({16'd0, led, push_buttons, dip_switches}), + .hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), + .hps_io_hps_io_emac1_inst_TXD0 (eth1_txd0), + .hps_io_hps_io_emac1_inst_TXD1 (eth1_txd1), + .hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), + .hps_io_hps_io_emac1_inst_RXD0 (eth1_rxd0), + .hps_io_hps_io_emac1_inst_RXD1 (eth1_rxd1), + .hps_io_hps_io_emac1_inst_TXD2 (eth1_txd2), + .hps_io_hps_io_emac1_inst_TXD3 (eth1_txd3), + .hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), + .hps_io_hps_io_emac1_inst_MDC (eth1_mdc), + .hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), + .hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), + .hps_io_hps_io_emac1_inst_RXD2 (eth1_rxd2), + .hps_io_hps_io_emac1_inst_RXD3 (eth1_rxd3), + .hps_io_hps_io_qspi_inst_IO0 (qspi_io0), + .hps_io_hps_io_qspi_inst_IO1 (qspi_io1), + .hps_io_hps_io_qspi_inst_IO2 (qspi_io2), + .hps_io_hps_io_qspi_inst_IO3 (qspi_io3), + .hps_io_hps_io_qspi_inst_SS0 (qspi_ss0), + .hps_io_hps_io_qspi_inst_CLK (qspi_clk), + .hps_io_hps_io_sdio_inst_CMD (sdio_cmd), + .hps_io_hps_io_sdio_inst_D0 (sdio_d0), + .hps_io_hps_io_sdio_inst_D1 (sdio_d1), + .hps_io_hps_io_sdio_inst_CLK (sdio_clk), + .hps_io_hps_io_sdio_inst_D2 (sdio_d2), + .hps_io_hps_io_sdio_inst_D3 (sdio_d3), + .hps_io_hps_io_usb1_inst_D0 (usb1_d0), + .hps_io_hps_io_usb1_inst_D1 (usb1_d1), + .hps_io_hps_io_usb1_inst_D2 (usb1_d2), + .hps_io_hps_io_usb1_inst_D3 (usb1_d3), + .hps_io_hps_io_usb1_inst_D4 (usb1_d4), + .hps_io_hps_io_usb1_inst_D5 (usb1_d5), + .hps_io_hps_io_usb1_inst_D6 (usb1_d6), + .hps_io_hps_io_usb1_inst_D7 (usb1_d7), + .hps_io_hps_io_usb1_inst_CLK (usb1_clk), + .hps_io_hps_io_usb1_inst_STP (usb1_stp), + .hps_io_hps_io_usb1_inst_DIR (usb1_dir), + .hps_io_hps_io_usb1_inst_NXT (usb1_nxt), + .hps_io_hps_io_uart0_inst_RX (uart0_rx), + .hps_io_hps_io_uart0_inst_TX (uart0_tx), + .hps_io_hps_io_uart1_inst_RX (uart1_rx), + .hps_io_hps_io_uart1_inst_TX (uart1_tx), + .hps_io_hps_io_i2c0_inst_SDA (i2c0_sda), + .hps_io_hps_io_i2c0_inst_SCL (i2c0_scl), + .hps_io_hps_io_trace_inst_CLK (trace_clk), + .hps_io_hps_io_trace_inst_D0 (trace_d0), + .hps_io_hps_io_trace_inst_D1 (trace_d1), + .hps_io_hps_io_trace_inst_D2 (trace_d2), + .hps_io_hps_io_trace_inst_D3 (trace_d3), + .hps_io_hps_io_trace_inst_D4 (trace_d4), + .hps_io_hps_io_trace_inst_D5 (trace_d5), + .hps_io_hps_io_trace_inst_D6 (trace_d6), + .hps_io_hps_io_trace_inst_D7 (trace_d7), + .hps_io_hps_io_gpio_inst_GPIO00 (gpio_gpio00), + .hps_io_hps_io_gpio_inst_GPIO17 (gpio_gpio17), + .hps_io_hps_io_gpio_inst_GPIO18 (gpio_gpio18), + .hps_io_hps_io_gpio_inst_GPIO22 (gpio_gpio22), + .hps_io_hps_io_gpio_inst_GPIO24 (gpio_gpio24), + .hps_io_hps_io_gpio_inst_GPIO26 (gpio_gpio26), + .hps_io_hps_io_gpio_inst_GPIO27 (gpio_gpio27), + .hps_io_hps_io_gpio_inst_GPIO35 (gpio_gpio35), + .hps_io_hps_io_gpio_inst_GPIO40 (gpio_gpio40), + .hps_io_hps_io_gpio_inst_GPIO41 (gpio_gpio41), + .hps_io_hps_io_gpio_inst_GPIO42 (gpio_gpio42), + .hps_io_hps_io_gpio_inst_GPIO43 (gpio_gpio43), + .sys_hps_h2f_reset_reset_n (sys_resetn), + .sys_gpio_external_connection_in_port ({rx_xcvr_status_s, 4'd0, push_buttons, 4'd0, dip_switches}), + .sys_gpio_external_connection_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, 12'd0, led}), + .axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk), + .axi_hdmi_tx_0_hdmi_if_h16_hsync (), + .axi_hdmi_tx_0_hdmi_if_h16_vsync (), + .axi_hdmi_tx_0_hdmi_if_h16_data_e (), + .axi_hdmi_tx_0_hdmi_if_h16_data (), + .axi_hdmi_tx_0_hdmi_if_h16_es_data (hdmi_data), + .axi_hdmi_tx_0_hdmi_if_h24_hsync (), + .axi_hdmi_tx_0_hdmi_if_h24_vsync (), + .axi_hdmi_tx_0_hdmi_if_h24_data_e (), + .axi_hdmi_tx_0_hdmi_if_h24_data (), + .axi_hdmi_tx_0_hdmi_if_h36_hsync (), + .axi_hdmi_tx_0_hdmi_if_h36_vsync (), + .axi_hdmi_tx_0_hdmi_if_h36_data_e (), + .axi_hdmi_tx_0_hdmi_if_h36_data (), + .sys_hdmi_pll_reconfig_to_pll_reconfig_to_pll (sys_hdmi_pll_reconfig_in), + .sys_hdmi_pll_reconfig_from_pll_reconfig_from_pll (sys_hdmi_pll_reconfig_out), + .sys_hdmi_pll_reconfig_reconfig_to_pll_reconfig_to_pll (sys_hdmi_pll_reconfig_reconfig_out), + .sys_hdmi_pll_reconfig_reconfig_from_pll_reconfig_from_pll (sys_hdmi_pll_reconfig_reconfig_in)); + +endmodule + +// *************************************************************************** +// ***************************************************************************