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fmcomms1: Update project to integrate the new util_wfifo

main
Adrian Costina 2015-06-10 15:16:17 +03:00
parent 8a1f4bf5f6
commit 97ab5e0ef7
13 changed files with 54 additions and 469 deletions
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1
projects/fmcomms1/ac701/system_bd.tcl
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@ -1,6 +1,5 @@
source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms1_bd.tcl
set_property -dict [list CONFIG.C_FIFO_SIZE {8}] $axi_ad9643_dma

70
projects/fmcomms1/ac701/system_top.v
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@ -163,33 +163,11 @@ module system_top (
output ref_clk_out_p;
output ref_clk_out_n;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
@ -225,36 +203,6 @@ module system_top (
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
@ -285,38 +233,20 @@ module system_top (
.mb_intr_08 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.ref_clk (ref_clk),
.mdio_io (phy_mdio),
.mdio_mdc (phy_mdc),

105
projects/fmcomms1/common/fmcomms1_bd.tcl
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@ -23,28 +23,6 @@
create_bd_port -dir O ref_clk
# dma interface
create_bd_port -dir O dac_clk
create_bd_port -dir O dac_valid_0
create_bd_port -dir O dac_enable_0
create_bd_port -dir I -from 63 -to 0 dac_ddata_0
create_bd_port -dir O dac_valid_1
create_bd_port -dir O dac_enable_1
create_bd_port -dir I -from 63 -to 0 dac_ddata_1
create_bd_port -dir I dac_dma_rd
create_bd_port -dir O -from 63 -to 0 dac_dma_rdata
create_bd_port -dir O adc_clk
create_bd_port -dir O adc_valid_0
create_bd_port -dir O adc_enable_0
create_bd_port -dir O -from 15 -to 0 adc_data_0
create_bd_port -dir O adc_valid_1
create_bd_port -dir O adc_enable_1
create_bd_port -dir O -from 15 -to 0 adc_data_1
create_bd_port -dir I adc_dma_wr
create_bd_port -dir I -from 31 -to 0 adc_dma_wdata
# dac peripherals
set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122]
@ -57,7 +35,10 @@
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma
set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122]
set_property -dict [list CONFIG.CH_DW {64} CONFIG.CH_CNT {2}] $util_upack_ad9122
# adc peripherals
@ -68,11 +49,21 @@
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_FIFO_SIZE {16}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
set util_cpack_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9643]
set_property -dict [list CONFIG.CH_DW {32} CONFIG.CH_CNT {2}] $util_cpack_ad9643
set util_ad9643_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9643_adc_fifo]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9643_adc_fifo
set_property -dict [list CONFIG.DIN_ADDR_WIDTH {4}] $util_ad9643_adc_fifo
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9643_adc_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {32}] $util_ad9643_adc_fifo
# reference clock
set refclk_clkgen [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 refclk_clkgen]
@ -91,6 +82,7 @@
ad_connect dac_clk axi_ad9122/dac_div_clk
ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk
ad_connect dac_clk util_upack_ad9122/dac_clk
ad_connect dac_clk_in_p axi_ad9122/dac_clk_in_p
ad_connect dac_clk_in_n axi_ad9122/dac_clk_in_n
@ -101,27 +93,32 @@
ad_connect dac_data_out_p axi_ad9122/dac_data_out_p
ad_connect dac_data_out_n axi_ad9122/dac_data_out_n
ad_connect axi_ad9122/dac_valid_0 dac_valid_0
ad_connect axi_ad9122/dac_enable_0 dac_enable_0
ad_connect axi_ad9122/dac_ddata_0 dac_ddata_0
ad_connect axi_ad9122/dac_valid_1 dac_valid_1
ad_connect axi_ad9122/dac_enable_1 dac_enable_1
ad_connect axi_ad9122/dac_ddata_1 dac_ddata_1
ad_connect axi_ad9122/dac_valid_0 util_upack_ad9122/dac_valid_0
ad_connect axi_ad9122/dac_enable_0 util_upack_ad9122/dac_enable_0
ad_connect axi_ad9122/dac_ddata_0 util_upack_ad9122/dac_data_0
ad_connect axi_ad9122/dac_valid_1 util_upack_ad9122/dac_valid_1
ad_connect axi_ad9122/dac_enable_1 util_upack_ad9122/dac_enable_1
ad_connect axi_ad9122/dac_ddata_1 util_upack_ad9122/dac_data_1
ad_connect axi_ad9122/dac_dunf axi_ad9122_dma/fifo_rd_underflow
ad_connect dac_dma_rd axi_ad9122_dma/fifo_rd_en
ad_connect dac_dma_rdata axi_ad9122_dma/fifo_rd_dout
ad_connect util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en
ad_connect util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout
ad_connect util_upack_ad9122/dac_sync axi_ad9122/dac_sync_in
# ad_connect axi_ad9122_dma/fifo_rd_xfer_req util_upack_ad9122/dma_xfer_in
# connections (adc)
p_sys_wfifo [current_bd_instance .] sys_wfifo 32 64
ad_connect adc_clk axi_ad9643/adc_clk
ad_connect adc_clk sys_wfifo/adc_clk
ad_connect adc_clk util_ad9643_adc_fifo/din_clk
ad_connect sys_200m_clk util_cpack_ad9643/adc_clk
ad_connect sys_200m_clk axi_ad9643/delay_clk
ad_connect sys_200m_clk axi_ad9643_dma/fifo_wr_clk
ad_connect sys_200m_clk sys_wfifo/dma_clk
ad_connect axi_ad9643/adc_rst sys_wfifo/adc_rst
ad_connect sys_200m_clk util_ad9643_adc_fifo/dout_clk
ad_connect adc_rst axi_ad9643/adc_rst
ad_connect adc_rst util_ad9643_adc_fifo/din_rst
ad_connect sys_cpu_resetn util_ad9643_adc_fifo/dout_rstn
ad_connect sys_cpu_reset util_cpack_ad9643/adc_rst
ad_connect adc_clk_in_p axi_ad9643/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9643/adc_clk_in_n
@ -130,20 +127,26 @@
ad_connect adc_data_in_p axi_ad9643/adc_data_in_p
ad_connect adc_data_in_n axi_ad9643/adc_data_in_n
ad_connect adc_valid_0 axi_ad9643/adc_valid_0
ad_connect adc_enable_0 axi_ad9643/adc_enable_0
ad_connect adc_data_0 axi_ad9643/adc_data_0
ad_connect adc_valid_1 axi_ad9643/adc_valid_1
ad_connect adc_enable_1 axi_ad9643/adc_enable_1
ad_connect adc_data_1 axi_ad9643/adc_data_1
ad_connect axi_ad9643/adc_dovf sys_wfifo/adc_wovf
ad_connect axi_ad9643/adc_valid_0 util_ad9643_adc_fifo/din_valid_0
ad_connect axi_ad9643/adc_enable_0 util_ad9643_adc_fifo/din_enable_0
ad_connect axi_ad9643/adc_data_0 util_ad9643_adc_fifo/din_data_0
ad_connect axi_ad9643/adc_valid_1 util_ad9643_adc_fifo/din_valid_1
ad_connect axi_ad9643/adc_enable_1 util_ad9643_adc_fifo/din_enable_1
ad_connect axi_ad9643/adc_data_1 util_ad9643_adc_fifo/din_data_1
ad_connect adc_dma_wr sys_wfifo/adc_wr
ad_connect adc_dma_wdata sys_wfifo/adc_wdata
ad_connect util_ad9643_adc_fifo/dout_valid_0 util_cpack_ad9643/adc_valid_0
ad_connect util_ad9643_adc_fifo/dout_enable_0 util_cpack_ad9643/adc_enable_0
ad_connect util_ad9643_adc_fifo/dout_data_0 util_cpack_ad9643/adc_data_0
ad_connect util_ad9643_adc_fifo/dout_valid_1 util_cpack_ad9643/adc_valid_1
ad_connect util_ad9643_adc_fifo/dout_enable_1 util_cpack_ad9643/adc_enable_1
ad_connect util_ad9643_adc_fifo/dout_data_1 util_cpack_ad9643/adc_data_1
ad_connect sys_wfifo/dma_wr axi_ad9643_dma/fifo_wr_en
ad_connect sys_wfifo/dma_wdata axi_ad9643_dma/fifo_wr_din
ad_connect sys_wfifo/dma_wovf axi_ad9643_dma/fifo_wr_overflow
ad_connect util_ad9643_adc_fifo/din_ovf axi_ad9643/adc_dovf
ad_connect util_cpack_ad9643/adc_valid axi_ad9643_dma/fifo_wr_en
ad_connect util_cpack_ad9643/adc_sync axi_ad9643_dma/fifo_wr_sync
ad_connect util_cpack_ad9643/adc_data axi_ad9643_dma/fifo_wr_din
ad_connect util_ad9643_adc_fifo/dout_ovf axi_ad9643_dma/fifo_wr_overflow
ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9643_dma/m_dest_axi_aresetn
@ -174,7 +177,7 @@
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
ad_connect sys_200m_clk ila_adc/clk
ad_connect sys_wfifo/dma_wr ila_adc/PROBE0
ad_connect sys_wfifo/dma_wdata ila_adc/PROBE1
ad_connect sys_200m_clk ila_adc/clk
ad_connect util_cpack_ad9643/adc_valid ila_adc/PROBE0
ad_connect util_cpack_ad9643/adc_data ila_adc/PROBE1

1
projects/fmcomms1/kc705/system_bd.tcl
View File

@ -1,5 +1,4 @@
source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms1_bd.tcl

70
projects/fmcomms1/kc705/system_top.v
View File

@ -187,15 +187,6 @@ module system_top (
output ref_clk_out_p;
output ref_clk_out_n;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -205,19 +196,6 @@ module system_top (
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
@ -248,36 +226,6 @@ module system_top (
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
@ -307,38 +255,20 @@ module system_top (
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.ref_clk (ref_clk),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),

1
projects/fmcomms1/vc707/system_bd.tcl
View File

@ -1,5 +1,4 @@
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms1_bd.tcl

70
projects/fmcomms1/vc707/system_top.v
View File

@ -179,15 +179,6 @@ module system_top (
output ref_clk_out_p;
output ref_clk_out_n;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -197,19 +188,6 @@ module system_top (
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
@ -238,36 +216,6 @@ module system_top (
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
@ -305,38 +253,20 @@ module system_top (
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.ref_clk (ref_clk),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),

1
projects/fmcomms1/zc702/system_bd.tcl
View File

@ -1,6 +1,5 @@
source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms1_bd.tcl

70
projects/fmcomms1/zc702/system_top.v
View File

@ -151,15 +151,6 @@ module system_top (
inout iic_scl;
inout iic_sda;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -173,19 +164,6 @@ module system_top (
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
wire [15:0] ps_intrs;
@ -218,36 +196,6 @@ module system_top (
.dio_o(gpio_i[15:0]),
.dio_p(gpio_bd));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt ;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
@ -273,38 +221,20 @@ module system_top (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),

1
projects/fmcomms1/zc706/system_bd.tcl
View File

@ -1,5 +1,4 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms1_bd.tcl

70
projects/fmcomms1/zc706/system_top.v
View File

@ -151,15 +151,6 @@ module system_top (
inout iic_scl;
inout iic_sda;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -173,19 +164,6 @@ module system_top (
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
@ -217,36 +195,6 @@ module system_top (
.dio_o(gpio_i[14:0]),
.dio_p(gpio_bd));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt ;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
@ -272,38 +220,20 @@ module system_top (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),

1
projects/fmcomms1/zed/system_bd.tcl
View File

@ -1,6 +1,5 @@
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_wfifo.tcl
source ../common/fmcomms1_bd.tcl
# Add extra register slice between ADC DMA and HP1 to meet timing

62
projects/fmcomms1/zed/system_top.v
View File

@ -171,15 +171,6 @@ module system_top (
input otg_vbusoc;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
@ -193,19 +184,6 @@ module system_top (
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
@ -261,36 +239,6 @@ module system_top (
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt ;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
@ -316,22 +264,12 @@ module system_top (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),